min.vhdl

数字钟的实现

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MIN is
    Port ( CLK ,clr: in std_logic;
		 EN: in std_logic;
		 COUT: out std_logic;
           MINSHI,MINGE : out std_logic_vector(3 downto 0));
end MIN;

architecture Behavioral of MIN is
begin
 process (clr,CLK)
  VARIABLE CNT1,CNT0:STD_LOGIC_VECTOR(3 DOWNTO 0); 
  begin
   if clr='0' then
       cnt1:="0000";
       cnt0:="0000"; 		 
	elsIF CLK='1' AND  CLK'event THEN
     IF EN='0' THEN
      IF CNT1="0101" AND CNT0="1000" THEN
	    CNT0:="1001";
	    COUT<='0';
      ELSIF CNT0<"1001" THEN 
         CNT0:=CNT0+1;
	 ELSE    
	    CNT0:="0000";
	    IF CNT1<"0101" THEN
	       CNT1:=CNT1+1;
	    ELSE
	       CNT1:="0000";
		  COUT<='1';
	    END IF;
      END IF;
    END IF;
  END IF;
        MINSHI<=CNT1;
	   MINGE<=CNT0;
end process;
end Behavioral;