miao.syr

数字钟的实现

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: miao.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : miao.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : miao
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : miao
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : miao.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/waitpast/dig_clk/miao.vhdl in Library work.
Architecture behavioral of Entity miao is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <miao> (Architecture <behavioral>).
Entity <miao> analyzed. Unit <miao> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <miao>.
    Related source file is E:/VHDL/waitpast/dig_clk/miao.vhdl.
INFO:Xst:1799 - State 0110 is never reached in FSM <CNT1>.
INFO:Xst:1799 - State 0101 is never reached in FSM <CNT1>.
    Found finite state machine <FSM_0> for signal <CNT1>.
    -----------------------------------------------------------------------
    | States             | 1                                              |
    | Transitions        | 1                                              |
    | Inputs             | 0                                              |
    | Outputs            | 0                                              |
    | Clock              | CLK (rising_edge)                              |
    | Clock enable       | $n0003 (positive)                              |
    | Reset              | CLR (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <COUT>.
    Found 4-bit comparator less for signal <$n0010> created at line 32.
    Found 4-bit adder for signal <$n0015> created at line 34.
    Found 4-bit register for signal <CNT0>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <miao> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CNT1> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 4-bit adder                       : 1
# Registers                        : 2
 1-bit register                    : 1
 4-bit register                    : 1
# Comparators                      : 1
 4-bit comparator less             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <COUT> (without init value) is constant in block <miao>.

Optimizing unit <miao> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block miao, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : miao.ngr
Top Level Output File Name         : miao
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 2
#      1-bit register              : 1
#      4-bit register              : 1
# Adders/Subtractors               : 1
#      4-bit adder                 : 1
# Comparators                      : 1
#      4-bit comparator less       : 1

Cell Usage :
# BELS                             : 18
#      GND                         : 1
#      LUT1                        : 1
#      LUT1_L                      : 4
#      LUT2_L                      : 3
#      LUT4                        : 1
#      LUT4_D                      : 1
#      MUXCY                       : 3
#      VCC                         : 1
#      XORCY                       : 3
# FlipFlops/Latches                : 4
#      FDCE                        : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 2
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       6  out of    768     0%  
 Number of Slice Flip Flops:             4  out of   1536     0%  
 Number of 4 input LUTs:                10  out of   1536     0%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.530ns (Maximum Frequency: 153.139MHz)
   Minimum input arrival time before clock: 4.686ns
   Maximum output required time after clock: 7.193ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               6.530ns (Levels of Logic = 6)
  Source:            CNT0_0 (FF)
  Destination:       CNT0_3 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: CNT0_0 to CNT0_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   1.085   1.440  CNT0_0 (CNT0_0)
     LUT1_L:I0->LO         1   0.549   0.000  Madd__n0015_inst_lut2_01 (Madd__n0015_inst_lut2_0)
     MUXCY:S->O            1   0.659   0.000  Madd__n0015_inst_cy_0 (Madd__n0015_inst_cy_0)
     MUXCY:CI->O           1   0.042   0.000  Madd__n0015_inst_cy_1 (Madd__n0015_inst_cy_1)
     MUXCY:CI->O           0   0.042   0.000  Madd__n0015_inst_cy_2 (Madd__n0015_inst_cy_2)
     XORCY:CI->O           1   0.420   1.035  Madd__n0015_inst_sum_3 (_n0015<3>)
     LUT2_L:I1->LO         1   0.549   0.000  _n0006<3>1 (_n0006<3>)
     FDCE:D                    0.709          CNT0_3
    ----------------------------------------
    Total                      6.530ns (4.055ns logic, 2.475ns route)
                                       (62.1% logic, 37.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              4.686ns (Levels of Logic = 2)
  Source:            ZANTING (PAD)
  Destination:       CNT0_3 (FF)
  Destination Clock: CLK rising

  Data Path: ZANTING to CNT0_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  ZANTING_IBUF (ZANTING_IBUF)
     LUT1:I0->O            4   0.549   1.440  CNT0_ClkEn_INV1 (CNT0_N31)
     FDCE:CE                   0.886          CNT0_0
    ----------------------------------------
    Total                      4.686ns (2.211ns logic, 2.475ns route)
                                       (47.2% logic, 52.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              7.193ns (Levels of Logic = 1)
  Source:            CNT0_3 (FF)
  Destination:       SECGE<3> (PAD)
  Source Clock:      CLK rising

  Data Path: CNT0_3 to SECGE<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   1.085   1.440  CNT0_3 (CNT0_3)
     OBUF:I->O                 4.668          SECGE_3_OBUF (SECGE<3>)
    ----------------------------------------
    Total                      7.193ns (5.753ns logic, 1.440ns route)
                                       (80.0% logic, 20.0% route)

=========================================================================
CPU : 2.66 / 4.01 s | Elapsed : 2.00 / 4.00 s
 
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Total memory usage is 55404 kilobytes