digclk.twr

数字钟的实现

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Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise dig_clk.ise -intstyle ise -e 3 -l 3 -s 5 -xml
digclk digclk.ncd -o digclk.twr digclk.pcf


Design file:              digclk.ncd
Physical constraint file: digclk.pcf
Device,speed:             xc3s400,-5 (PRODUCTION 1.37 2005-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
lcd_en      |    9.585(R)|clk_BUFGP         |   0.000|
sound       |   10.420(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.430|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed May 16 17:45:37 2007
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Peak Memory Usage: 107 MB