min.syr

数字钟的实现

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: min.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : min.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : min
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : min
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : min.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/dig_clk/MIN.vhdl in Library work.
Architecture behavioral of Entity min is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <min> (Architecture <behavioral>).
Entity <min> analyzed. Unit <min> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <min>.
    Related source file is e:/vhdl/dig_clk/MIN.vhdl.
    Found 1-bit register for signal <COUT>.
    Found 4-bit comparator less for signal <$n0008> created at line 36.
    Found 4-bit comparator less for signal <$n0010> created at line 31.
    Found 4-bit adder for signal <$n0011> created at line 37.
    Found 4-bit adder for signal <$n0015> created at line 33.
    Found 4-bit register for signal <CNT0>.
    Found 4-bit register for signal <CNT1>.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <min> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 4-bit adder                       : 2
# Registers                        : 3
 1-bit register                    : 1
 4-bit register                    : 2
# Comparators                      : 2
 4-bit comparator less             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <min> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block min, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : min.ngr
Top Level Output File Name         : min
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 3
#      1-bit register              : 1
#      4-bit register              : 2
# Adders/Subtractors               : 2
#      4-bit adder                 : 2
# Comparators                      : 2
#      4-bit comparator less       : 2

Cell Usage :
# BELS                             : 37
#      GND                         : 1
#      LUT1_L                      : 8
#      LUT2_L                      : 3
#      LUT3                        : 2
#      LUT3_D                      : 1
#      LUT3_L                      : 1
#      LUT4                        : 3
#      LUT4_D                      : 2
#      LUT4_L                      : 3
#      MUXCY                       : 6
#      VCC                         : 1
#      XORCY                       : 6
# FlipFlops/Latches                : 9
#      FDCE                        : 8
#      FDE                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 2
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      14  out of    768     1%  
 Number of Slice Flip Flops:             9  out of   1536     0%  
 Number of 4 input LUTs:                23  out of   1536     1%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 7.110ns (Maximum Frequency: 140.647MHz)
   Minimum input arrival time before clock: 6.738ns
   Maximum output required time after clock: 7.661ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               7.110ns (Levels of Logic = 2)
  Source:            CNT0_0 (FF)
  Destination:       COUT (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: CNT0_0 to COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   1.085   1.440  CNT0_0 (CNT0_0)
     LUT3_D:I0->O          5   0.549   1.566  Ker7441 (N746)
     LUT4:I0->O            1   0.549   1.035  _n0006 (_n0006)
     FDE:CE                    0.886          COUT
    ----------------------------------------
    Total                      7.110ns (3.069ns logic, 4.041ns route)
                                       (43.2% logic, 56.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Offset:              6.738ns (Levels of Logic = 3)
  Source:            CLR (PAD)
  Destination:       COUT (FF)
  Destination Clock: CLK rising

  Data Path: CLR to COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.776   1.908  CLR_IBUF (CLR_IBUF)
     LUT3:I2->O            1   0.549   1.035  _n0006_SW0 (N811)
     LUT4:I2->O            1   0.549   1.035  _n0006 (_n0006)
     FDE:CE                    0.886          COUT
    ----------------------------------------
    Total                      6.738ns (2.760ns logic, 3.978ns route)
                                       (41.0% logic, 59.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Offset:              7.661ns (Levels of Logic = 1)
  Source:            CNT0_3 (FF)
  Destination:       MINGE<3> (PAD)
  Source Clock:      CLK rising

  Data Path: CNT0_3 to MINGE<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.085   1.908  CNT0_3 (CNT0_3)
     OBUF:I->O                 4.668          MINGE_3_OBUF (MINGE<3>)
    ----------------------------------------
    Total                      7.661ns (5.753ns logic, 1.908ns route)
                                       (75.1% logic, 24.9% route)

=========================================================================
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Total memory usage is 55404 kilobytes