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📄 xst.xmsgs

📁 数字钟的实现
💻 XMSGS
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf</arg>&quot; line <arg fmt="%d" index="2">14</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">F:/FPGA/VHDL/waitpast/dig_clk_lcd/digclk.vhf</arg>&quot; line <arg fmt="%d" index="2">15</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="warning" file="Xst" num="819" delta="unknown" >&quot;<arg fmt="%s" index="1">F:/FPGA/VHDL/waitpast/dig_clk_lcd/FEN_SOUND.vhdl</arg>&quot; line <arg fmt="%d" index="2">33</arg>: The following signals are missing in the process sensitivity list:
<arg fmt="%s" index="3">y</arg>.
</msg>

<msg type="warning" file="Xst" num="790" delta="unknown" >&quot;<arg fmt="%s" index="1">F:/FPGA/VHDL/waitpast/dig_clk_lcd/LCD1602.vhd</arg>&quot; line <arg fmt="%d" index="2">139</arg>: Index value(s) does not match array range, simulation mismatch.
</msg>

<msg type="warning" file="Xst" num="1780" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">m</arg>&gt; is never used or assigned.
</msg>

<msg type="warning" file="Xst" num="1781" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">cgram&lt;0:15&gt;</arg>&gt; is used but never assigned. Tied to default value.
</msg>

<msg type="warning" file="Xst" num="653" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">cgram&lt;18&gt;</arg>&gt; is used but never assigned. Tied to value <arg fmt="%s" index="2">00101101</arg>.
</msg>

<msg type="warning" file="Xst" num="653" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">cgram&lt;21&gt;</arg>&gt; is used but never assigned. Tied to value <arg fmt="%s" index="2">00101101</arg>.
</msg>

<msg type="warning" file="Xst" num="1781" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">cgram&lt;24:30&gt;</arg>&gt; is used but never assigned. Tied to default value.
</msg>

<msg type="info" file="Xst" num="1767" delta="unknown" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
</msg>

<msg type="warning" file="Xst" num="1989" delta="unknown" >Unit &lt;<arg fmt="%s" index="1">fpq1S</arg>&gt;: instances &lt;<arg fmt="%s" index="2">Mcompar__n0002</arg>&gt;, &lt;<arg fmt="%s" index="3">Mcompar__n0005</arg>&gt; of unit &lt;<arg fmt="%s" index="4">LPM_COMPARE_7</arg>&gt; are equivalent, second instance is removed
</msg>

<msg type="warning" file="Xst" num="2041" delta="unknown" >Unit <arg fmt="%s" index="1">digclk</arg>: <arg fmt="%d" index="2">1</arg> internal tristate is replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>

<msg type="warning" file="Xst" num="1710" delta="unknown" >FF/Latch  &lt;<arg fmt="%s" index="1">XLXI_19/CNT1_3</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">digclk</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1710" delta="unknown" >FF/Latch  &lt;<arg fmt="%s" index="1">CNT1_3</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">MIN</arg>&gt;.
</msg>

<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>

</messages>

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