clock.map.qmsg

VHDL实现数字时钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 01 18:52:03 2007 " "Info: Processing started: Tue May 01 18:52:03 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "E:/CPLDprogram/综合实验/数字时钟/clock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decode47.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decode47.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decode47-behave " "Info: Found design unit 1: decode47-behave" {  } { { "decode47.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/decode47.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decode47 " "Info: Found entity 1: decode47" {  } { { "decode47.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/decode47.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sel.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sel.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sel-behave " "Info: Found design unit 1: sel-behave" {  } { { "sel.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/sel.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sel " "Info: Found entity 1: sel" {  } { { "sel.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/sel.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen60-behave " "Info: Found design unit 1: fen60-behave" {  } { { "fen60.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen60.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fen60 " "Info: Found entity 1: fen60" {  } { { "fen60.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen60.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen24-behave " "Info: Found design unit 1: fen24-behave" {  } { { "fen24.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen24.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fen24 " "Info: Found entity 1: fen24" {  } { { "fen24.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen24.vhd" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen1-behave " "Info: Found design unit 1: fen1-behave" {  } { { "fen1.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen1.vhd" 23 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fen1 " "Info: Found entity 1: fen1" {  } { { "fen1.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen1.vhd" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen100.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen100.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen100-behave " "Info: Found design unit 1: fen100-behave" {  } { { "fen100.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen100.vhd" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fen100 " "Info: Found entity 1: fen100" {  } { { "fen100.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/fen100.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode47 decode47:inst6 " "Info: Elaborating entity \"decode47\" for hierarchy \"decode47:inst6\"" {  } { { "clock.bdf" "inst6" { Schematic "E:/CPLDprogram/综合实验/数字时钟/clock.bdf" { { 0 672 816 96 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sel sel:inst5 " "Info: Elaborating entity \"sel\" for hierarchy \"sel:inst5\"" {  } { { "clock.bdf" "inst5" { Schematic "E:/CPLDprogram/综合实验/数字时钟/clock.bdf" { { -16 424 568 176 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Error" "EVRFX_VHDL_VAL_OUT_OF_CONSTRAINT_ERR" "sel.vhd(63) " "Error (10528): VHDL Signal or Variable Assignment Statement error at sel.vhd(63): value assigned to signal or variable must belong to signal or variable range" {  } { { "sel.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/sel.vhd" 63 0 0 } }  } 0 10528 "VHDL Signal or Variable Assignment Statement error at %1!s!: value assigned to signal or variable must belong to signal or variable range" 0 0}
{ "Error" "EVRFX_VHDL_VAL_OUT_OF_CONSTRAINT_ERR" "sel.vhd(65) " "Error (10528): VHDL Signal or Variable Assignment Statement error at sel.vhd(65): value assigned to signal or variable must belong to signal or variable range" {  } { { "sel.vhd" "" { Text "E:/CPLDprogram/综合实验/数字时钟/sel.vhd" 65 0 0 } }  } 0 10528 "VHDL Signal or Variable Assignment Statement error at %1!s!: value assigned to signal or variable must belong to signal or variable range" 0 0}
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "sel:inst5 " "Error: Can't elaborate user hierarchy \"sel:inst5\"" {  } { { "clock.bdf" "inst5" { Schematic "E:/CPLDprogram/综合实验/数字时钟/clock.bdf" { { -16 424 568 176 "inst5" "" } } } }  } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue May 01 18:52:04 2007 " "Error: Processing ended: Tue May 01 18:52:04 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}