程序如下：.txt

用VHDL设计一个4位二进制并行半加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  DISPLAY  IS
PORT(CLK:IN STD_LOGIC;
ADDR: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
AIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
BIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
COM:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY DISPLAY;
ARCHITECTURE ART OF DISPLAY IS 
   SIGNAL AA,BB,SINT:STD_LOGIC_VECTOR(4 DOWNTO 0);
   SIGNAL CNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL BCD:STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL SUM0: STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL SUM1: STD_LOGIC_VECTOR(3 DOWNTO 0);

      BEGIN
   AA<='0'&AIN;
   BB<='0'&BIN;
SINT<=AA+BB;
SUM0<=SINT(3 DOWNTO 0);
SUM1<="000"&SINT(4);

PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
  IF CNT="111"THEN
    CNT<="000";
ELSE
  CNT<=CNT+'1';
END IF;
  END IF;
  END PROCESS;
  COM<=CNT;
  PROCESS(CNT) IS
  BEGIN
  CASE CNT IS
    WHEN"000"=>BCD<=AIN(3 DOWNTO 0);
    WHEN"010"=>BCD<=BIN(3 DOWNTO 0);
  
  WHEN"100"=>BCD<=SINT(3 DOWNTO 0);
WHEN"101"=>BCD<="000"&SINT(4);
WHEN OTHERS=>BCD<="0000";
END CASE;
CASE BCD IS
  WHEN "0000" =>SEG<="00111111";
WHEN "0001" =>SEG<="00000110";
WHEN "0010" =>SEG<="01011011";
WHEN "0011" =>SEG<="01001111";
WHEN "0100" =>SEG<="01100110";
WHEN "0101" =>SEG<="01101101";
WHEN "0110" =>SEG<="01111101";
WHEN "0111" =>SEG<="00000111";
WHEN "1000" =>SEG<="01111111";
WHEN "1001" =>SEG<="01101111";
WHEN "1010" =>SEG<="01110111";
WHEN "1011" =>SEG<="01111100";
WHEN "1100" =>SEG<="00111001";
WHEN "1101" =>SEG<="01011110";
WHEN "1110" =>SEG<="01111001";
WHEN "1111" =>SEG<="01110001";
WHEN OTHERS=>SEG<="00000000";
END CASE;
END PROCESS;
END ARCHITECTURE ART;