📄 freqdiv.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\freqdiv.rpt
freqdiv
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 6/ 48( 12%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\freqdiv.rpt
freqdiv
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\freqdiv.rpt
freqdiv
** EQUATIONS **
clk : INPUT;
-- Node name is 'clk_out'
-- Equation name is 'clk_out', type is output
clk_out = _LC4_B3;
-- Node name is ':11' = 'num0'
-- Equation name is 'num0', location is LC5_B3, type is buried.
num0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !num0 & !num3
# _LC2_B3 & !num0;
-- Node name is ':10' = 'num1'
-- Equation name is 'num1', location is LC7_B3, type is buried.
num1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC8_B3 & !num0 & num1
# _LC8_B3 & num0 & !num1;
-- Node name is ':9' = 'num2'
-- Equation name is 'num2', location is LC6_B3, type is buried.
num2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC8_B3 & !num1 & num2
# _LC8_B3 & !num0 & num2
# _LC8_B3 & num0 & num1 & !num2;
-- Node name is ':8' = 'num3'
-- Equation name is 'num3', location is LC1_B3, type is buried.
num3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_B11 & !num3
# _LC3_B3 & !num3
# _LC2_B3 & !_LC3_B3 & num3;
-- Node name is ':7' = 'num4'
-- Equation name is 'num4', location is LC2_B11, type is buried.
num4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC8_B3 & !num3 & num4
# !_LC3_B3 & _LC8_B3 & num4
# _LC3_B3 & _LC8_B3 & num3 & !num4;
-- Node name is ':6' = 'num5'
-- Equation name is 'num5', location is LC5_B11, type is buried.
num5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC3_B11 & _LC8_B3 & num5
# _LC3_B11 & _LC8_B3 & !num5;
-- Node name is ':5' = 'num6'
-- Equation name is 'num6', location is LC6_B11, type is buried.
num6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC8_B3 & !num5 & num6
# !_LC3_B11 & _LC8_B3 & num6
# _LC3_B11 & _LC8_B3 & num5 & !num6;
-- Node name is ':4' = 'num7'
-- Equation name is 'num7', location is LC8_B11, type is buried.
num7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC8_B3 & !num6 & num7
# !_LC7_B11 & _LC8_B3 & num7
# _LC7_B11 & _LC8_B3 & num6 & !num7;
-- Node name is '|LPM_ADD_SUB:183|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ009);
_EQ009 = num0 & num1 & num2;
-- Node name is '|LPM_ADD_SUB:183|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ010);
_EQ010 = _LC3_B3 & num3 & num4;
-- Node name is '|LPM_ADD_SUB:183|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ011);
_EQ011 = _LC3_B11 & num5;
-- Node name is ':2'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !_LC1_B11 & !_LC4_B3 & !num3
# !_LC2_B3 & !_LC4_B3 & num3
# _LC1_B11 & _LC4_B3 & !num3
# _LC2_B3 & _LC4_B3 & num3
# _LC1_B11 & _LC2_B3 & _LC4_B3;
-- Node name is '~64~1'
-- Equation name is '~64~1', location is LC4_B11, type is buried.
-- synthesized logic cell
_LC4_B11 = LCELL( _EQ013);
_EQ013 = num4
# num5
# num6
# num7;
-- Node name is '~64~2'
-- Equation name is '~64~2', location is LC1_B11, type is buried.
-- synthesized logic cell
_LC1_B11 = LCELL( _EQ014);
_EQ014 = _LC4_B11
# !_LC3_B3;
-- Node name is '~81~1'
-- Equation name is '~81~1', location is LC2_B3, type is buried.
-- synthesized logic cell
_LC2_B3 = LCELL( _EQ015);
_EQ015 = _LC4_B11
# num0
# !num2
# !num1;
-- Node name is '~226~1'
-- Equation name is '~226~1', location is LC8_B3, type is buried.
-- synthesized logic cell
_LC8_B3 = LCELL( _EQ016);
_EQ016 = _LC1_B11 & !num3
# _LC2_B3 & num3
# _LC1_B11 & _LC2_B3;
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\freqdiv.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,246K
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