📄 dds1.rpt
字号:
^
C
R R R R R R O
E E E E E E N
S S S S S S V G G G G F
E E E E E E C N N N N _ ^
R R R R R R C D D D D # D n
V V V V V V c I c I I I c I c c c c T O C
E E E E E E o N o N N N o N o o o o C N E
D D D D D D 7 T 6 T T T 5 T 4 3 2 1 K E O
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/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | co0
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
RESERVED | 16 70 | cs2
int | 17 69 | cs4
cs1 | 18 68 | GNDINT
clk | 19 67 | ko0
VCCINT | 20 66 | ko1
RESERVED | 21 65 | ko2
RESERVED | 22 EPF10K10LC84-4 64 | ko3
RESERVED | 23 63 | VCCINT
RESERVED | 24 62 | key0
cs3 | 25 61 | key1
GNDINT | 26 60 | key2
RESERVED | 27 59 | key3
RESERVED | 28 58 | data0
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | data1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G G G G V G k d d d d d d
C n E E E E E C N N N N C N v a a a a a a
C C S S S S S C D D D D C D t t t t t t
I O E E E E E I I I I I I I a a a a a a
N N R R R R R N N N N N N N 7 6 5 4 3 2
T F V V V V V T T T T T T T
I E E E E E
G D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 10/22( 45%)
A2 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 4/22( 18%)
A3 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 6/22( 27%)
A4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
A5 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 0/2 10/22( 45%)
A6 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 5/22( 22%)
A7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
A8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 7/22( 31%)
A9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
A10 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 7/22( 31%)
A11 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 8/22( 36%)
A12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 5/22( 22%)
A13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 16/22( 72%)
A16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
A17 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 16/22( 72%)
A18 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 16/22( 72%)
A19 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 14/22( 63%)
A20 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 15/22( 68%)
A21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
A23 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
A24 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
B1 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 3/22( 13%)
B2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B3 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B4 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B5 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 4/22( 18%)
B7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B8 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B13 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
B14 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 8/22( 36%)
B16 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
B17 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
B22 7/ 8( 87%) 5/ 8( 62%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
B23 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
B24 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 4/22( 18%)
C3 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C10 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
C12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C20 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
C21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C22 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
C24 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
B25 8/8 (100%) 0/8 ( 0%) 4/8 ( 50%) 0/2 2/2 9/22( 40%)
C25 8/8 (100%) 1/8 ( 12%) 4/8 ( 50%) 0/2 2/2 9/22( 40%)
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 31/53 ( 58%)
Total logic cells used: 298/576 ( 51%)
Total embedded cells used: 16/24 ( 66%)
Total EABs used: 2/3 ( 66%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 1007/2304 ( 43%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 26
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 298
Total flipflops required: 138
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 42/ 576 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 3 7 8 8 8 2 8 8 8 8 8 0 8 1 8 8 8 8 8 8 8 8 7 8 172/0
B: 5 1 8 8 7 0 8 5 0 0 0 0 8 8 8 0 2 4 0 0 0 8 7 2 4 85/8
C: 0 0 8 8 1 0 1 0 0 6 0 1 8 1 0 0 0 0 0 0 4 1 2 0 8 41/8
Total: 13 4 23 24 16 8 11 13 8 14 8 9 16 17 9 8 10 12 8 8 12 17 17 9 20 298/16
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- INPUT 0 0 0 78 clk
62 - - C -- INPUT 0 0 0 5 key0
61 - - C -- INPUT 0 0 0 5 key1
60 - - C -- INPUT 0 0 0 5 key2
59 - - C -- INPUT 0 0 0 5 key3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
73 - - A -- OUTPUT 0 1 0 0 co0
78 - - - 24 OUTPUT 0 1 0 0 co1
79 - - - 24 OUTPUT 0 1 0 0 co2
80 - - - 23 OUTPUT 0 1 0 0 co3
81 - - - 22 OUTPUT 0 1 0 0 co4
83 - - - 13 OUTPUT 0 1 0 0 co5
3 - - - 12 OUTPUT 0 1 0 0 co6
5 - - - 05 OUTPUT 0 1 0 0 co7
18 - - A -- OUTPUT 0 0 0 0 cs1
70 - - A -- OUTPUT 0 0 0 0 cs2
25 - - B -- OUTPUT 0 0 0 0 cs3
69 - - A -- OUTPUT 0 1 0 0 cs4
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