test_double3.tan.rpt

DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制

+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C3T144C8        ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Minimum tpd to report                                 ; 0.0NS              ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; Off                ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                             ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                              ; To                                                                                                          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 7.955 ns                         ; WR                                ; BUS_51:inst9|RAMTMP3[7]                                                                                     ;            ; CLK      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 11.464 ns                        ; generator_reg81:inst6|TEMP_Q_1[7] ; Q1[7]                                                                                                       ; CLK        ;          ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 3.179 ns                         ; P0[0]                             ; BUS_51:inst9|LATCH_ADDRES[0]                                                                                ;            ; ALE      ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 6.457 ns                         ; BUS_51:inst9|P0_OUT[7]            ; P0[7]                                                                                                       ; CLK        ;          ; 0            ;
; Clock Setup: 'CLK'           ; N/A                                      ; None          ; 92.03 MHz ( period = 10.866 ns ) ; BUS_51:inst9|RAMTMP3[7]           ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg7 ; CLK        ; CLK      ; 0            ;
; Clock Hold: 'CLK'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; BUS_51:inst9|RAMTMP0[7]           ; generator_accB:inst3|REG_Q[15]                                                                              ; CLK        ; CLK      ; 152          ;
; Total number of failed paths ;                                          ;               ;                                  ;                                   ;                                                                                                             ;            ;          ; 152          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+