mux2s.vhd

来自「DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2S IS
PORT(S1:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
	S2:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
	M:OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
	CLK:IN STD_LOGIC
);
END MUX2S;
ARCHITECTURE ART OF MUX2S IS
BEGIN
M<=S1 WHEN CLK='1' ELSE
   S2 WHEN CLK='0';
	--	IF CLK='1' THEN
	--	    M<=S1; 
	--    ELSE 
    --        M<=S2;

		--END IF;
	--END PROCESS;
END ART;