test_double3.tan.rpt
来自「DDS锯齿波发生器: 开发平台:maxplus+FPGA 功能: 输出X路扫」· RPT 代码 · 共 229 行 · 第 1/5 页
RPT
229 行
; N/A ; 119.08 MHz ( period = 8.398 ns ) ; BUS_51:inst9|RAMTMP2[2] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg3 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 120.80 MHz ( period = 8.278 ns ) ; generator_accB:inst3|REG_Q[11] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg4 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 122.62 MHz ( period = 8.155 ns ) ; generator_accB:inst3|REG_Q[12] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg5 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 122.94 MHz ( period = 8.134 ns ) ; generator_accB:inst3|REG_Q[13] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg6 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 123.02 MHz ( period = 8.129 ns ) ; generator_accB:inst3|REG_Q[10] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg3 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 124.13 MHz ( period = 8.056 ns ) ; BUS_51:inst9|RAMTMP2[0] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg1 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 124.88 MHz ( period = 8.008 ns ) ; BUS_51:inst9|RAMTMP2[3] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg4 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 126.09 MHz ( period = 7.931 ns ) ; generator_accB:inst3|REG_Q[15] ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg8 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg5 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg6 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg7 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg8 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[6] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg5 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg6 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg7 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg8 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[5] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg5 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg6 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg7 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg8 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[4] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg1 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg2 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg3 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg4 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg5 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg6 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg7 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg8 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[3] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 197.01 MHz ( period = 5.076 ns ) ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|ram_block1a7~porta_address_reg0 ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_ccr:auto_generated|q_a[2] ; CLK ; CLK ; None ; None ;
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