datachoose.v

来自「基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Ve」· Verilog 代码 · 共 84 行

//DataChoose.v	 	待显示数据选择模块	2006-11-5	version:1.4		作者：田世坤
//输入：
//		
//		
//输出：

module DataChoose(	D7, D6, D5, D4, D3, D2, D1, D0, 
					DD7, DD6, DD5, DD4, DD3, DD2, DD1, DD0, 
					DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0,
					DSW7, DSW6, DSW5, DSW4, DSW3, DSW2, DSW1, DSW0,
					State, 
					Disp7, Disp6, Disp5, Disp4, Disp3, Disp2, Disp1, Disp0);
					
input [3:0] D7, D6, D5, D4, D3, D2, D1, D0;
input [3:0] DD7, DD6, DD5, DD4, DD3, DD2, DD1, DD0;
input [3:0] DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0;
input [3:0] DSW7, DSW6, DSW5, DSW4, DSW3, DSW2, DSW1, DSW0;
input [3:0] State;
output [3:0] Disp7, Disp6, Disp5, Disp4, Disp3, Disp2, Disp1, Disp0;
reg [3:0] Disp7, Disp6, Disp5, Disp4, Disp3, Disp2, Disp1, Disp0;


always 
begin
		case(State)
			4'b1110:	
				begin
					Disp7 = D7;
					Disp6 = D6;
					Disp5 = D5;
					Disp4 = D4;
					Disp3 = D3;
					Disp2 = D2;
					Disp1 = D1;
					Disp0 = D0;
				end
			4'b1101:
				begin
					Disp7 = DD7;
					Disp6 = DD6;
					Disp5 = DD5;
					Disp4 = DD4;
					Disp3 = DD3;
					Disp2 = DD2;
					Disp1 = DD1;
					Disp0 = DD0;
				end
			4'b1011:	
				begin
					Disp7 = DA7;
					Disp6 = DA6;
					Disp5 = DA5;
					Disp4 = DA4;
					Disp3 = DA3;
					Disp2 = DA2;
					Disp1 = DA1;
					Disp0 = DA0;
				end
			4'b0111:	
				begin
					Disp7 = DSW7;
					Disp6 = DSW6;
					Disp5 = DSW5;
					Disp4 = DSW4;
					Disp3 = DSW3;
					Disp2 = DSW2;
					Disp1 = DSW1;
					Disp0 = DSW0;
				end
			default:
				begin
					Disp7 = D7;
					Disp6 = D6;
					Disp5 = D5;
					Disp4 = D4;
					Disp3 = D3;
					Disp2 = D2;
					Disp1 = D1;
					Disp0 = D0;
				end
		endcase
end

endmodule