numclock.v

来自「基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Ve」· Verilog 代码 · 共 59 行

//NumClock.v	 	NumClock总模块	 	2006-11-3	version:1.0		作者：田世坤
//输入：
//		
//		
//输出：

module NumClock(ClkIn10mhz, Reset, KeyIn,
			SCK, SDA, CS, LedOut, U5Dir_KeyIn, U9Dir_SerialOut, AlarmR, SoundReport);
input ClkIn10mhz, Reset;
input [7:0] KeyIn;
output SCK, SDA, CS;
output [3:0] LedOut;
output U5Dir_KeyIn, U9Dir_SerialOut;
output AlarmR, SoundReport;

wire Clk7219, ClkIn;
wire [3:0] D7, D6, D5, D4, D3, D2, D1, D0;
wire [3:0] DD7, DD6, DD5, DD4, DD3, DD2, DD1, DD0;
wire [3:0] DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0;
wire [3:0] DSW7, DSW6, DSW5, DSW4, DSW3, DSW2, DSW1, DSW0;
wire [3:0] Disp7, Disp6, Disp5, Disp4, Disp3, Disp2, Disp1, Disp0;
wire [7:0] KeyData;			
wire[11:0] State;
wire AlarmOut, AlarmEn, ClkOut1Hz, ClkOutLow, ClkOutHigh, ClkOut4Hz, ClkOutMid;

assign AlarmR = AlarmOut & ClkOut1Hz & ClkOutLow & ClkOut4Hz;

assign U5Dir_KeyIn = 0;
assign U9Dir_SerialOut = 1;
assign LedOut = State[11:8];

ClockOut U1(ClkIn10mhz, Reset,
				Clk7219, ClkIn, ClkOut1Hz, ClkOutLow, ClkOutHigh, ClkOut4Hz, ClkOutMid);
				
Key U2(ClkIn,KeyIn,KeyData);

KeyStates U3(ClkIn, Reset, KeyData, 
				AlarmEn, State);

MainControl U4(ClkIn, Reset, KeyData, State, ClkOut1Hz, ClkOutLow, ClkOutHigh, ClkOutMid,
			D7, D6, D5, D4, D3, D2, D1, D0, DD7, DD6, DD5, DD4, DD3, DD2, DD1, DD0, SoundReport);
			
Alarm U5(ClkIn, Reset, KeyData, State, AlarmEn, D7, D6, D5, D4, D3, D2, D1, D0,  
			DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0, AlarmOut);
			
StopWatch U6(ClkIn, KeyData, State, 
			DSW7, DSW6, DSW5, DSW4, DSW3, DSW2, DSW1, DSW0);
			
DataChoose U7(	D7, D6, D5, D4, D3, D2, D1, D0, 
				DD7, DD6, DD5, DD4, DD3, DD2, DD1, DD0, 
				DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0,
				DSW7, DSW6, DSW5, DSW4, DSW3, DSW2, DSW1, DSW0,
				State[11:8], 
				Disp7, Disp6, Disp5, Disp4, Disp3, Disp2, Disp1, Disp0);
			
Display7219 U8(Clk7219, Reset, ClkIn, Disp7, Disp6, Disp5, Disp4, Disp3, Disp2, Disp1, Disp0, State[7:0], 
				SCK, SDA, CS);
				
endmodule