key.v

来自「基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Ve」· Verilog 代码 · 共 42 行

//Key.v		按键处理模块　v0.93	2006-04-24

module Key(ClkIn,KeyIn,KeyOut);
  input ClkIn;
  input [7:0] KeyIn;
  output [7:0] KeyOut;
  reg [7:0] KeyOut;
  
  reg [10:0] Scan;

  parameter LEN=500;//去抖周期数
  //parameter LEN=10;  

  integer i=0;

  always @(negedge ClkIn)
    begin
	    if(KeyIn!=8'hff)
	    begin
			if(Scan!=LEN) 
				Scan <= Scan+1'b1; 
			else  
				i=i+1;
	    end
	    else
	        begin
				i = 0;
	          	if(Scan!=0) Scan<=Scan-1'b1;
	        end
	
		if(i==1)
			begin
				KeyOut <= KeyIn;
			end
		else
			begin
				KeyOut <= 8'hff;
			end
    end

endmodule