clockout.v

基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计&

//ClockOut.v	 	时钟变换模块		2006-8-28	version:1.5		作者：田世坤
//输入：
//		
//		
//输出：

module ClockOut(ClkIn10mhz, Reset,
				ClkOut7219, ClkOutTime, ClkOut1Hz, ClkOutLow, ClkOutHigh, ClkOut4Hz, ClkOutMid);
	input ClkIn10mhz;
	input Reset; 
	output ClkOut7219, ClkOutTime, ClkOut1Hz, ClkOutLow, ClkOutHigh, ClkOut4Hz, ClkOutMid;
	reg ClkOut7219, ClkOutTime, ClkOut1Hz, ClkOutLow, ClkOutHigh, ClkOut4Hz, ClkOutMid;
		
	//parameter p1 = 3'd4;	//参数p1为分频的次数，改变这个参数来改变输出时钟ClkOut7219, ClkOut7219=10Mhz/p1.
	parameter p2 = 10'd1000;	//参数p2为分频的次数，改变这个参数来改变输出时钟ClkOutTime, ClkOutTime=10Mhz/p2.
	parameter p3 = 25'd20000000;//参数p3为分频的次数，改变这个参数来改变输出时钟ClkOut3, ClkOut3=10Mhz/p3.
	parameter p4 = 15'd20000;//参数p3为分频的次数，改变这个参数来改变输出时钟ClkOut3, ClkOut3=10Mhz/p3.
	parameter p5 = 13'd5000;//参数p3为分频的次数，改变这个参数来改变输出时钟ClkOut3, ClkOut3=10Mhz/p3.
	parameter p6 = 23'd5000000;//参数p3为分频的次数，改变这个参数来改变输出时钟ClkOut3, ClkOut3=10Mhz/p3.
	parameter p7 = 14'd10000;//参数p3为分频的次数，改变这个参数来改变输出时钟ClkOut3, ClkOut3=10Mhz/p3.
	//integer i1 = 1;
	integer i2 = 1;
	integer i3 = 1;
	integer i4 = 1;
	integer i5 = 1;	
	integer i6 = 1;	
	integer i7 = 1;
	
always @ (posedge ClkIn10mhz)
	if(!Reset)
	begin
		ClkOut7219 <= 1'b0;
		ClkOutTime <= 1'b0;
		ClkOut1Hz <= 1'b0;
		ClkOutLow <= 1'b0;
		ClkOutHigh <= 1'b0;
		ClkOut4Hz <= 1'b0;
		ClkOutMid <= 1'b0;
	end
	else
	begin
		//i1 <= i1 + 1;
		i2 <= i2 + 1;
		i3 <= i3 + 1;
		i4 <= i4 + 1;
		i5 <= i5 + 1;
		i6 <= i6 + 1;
		i7 <= i7 + 1;
		
		ClkOut7219 = ~ClkOut7219;
		
		if(i2 == (p2>>1))
		begin
			ClkOutTime <= 1'b1;
		end
		else if(i2 == p2)
		begin
			ClkOutTime <= 1'b0;
			i2 <= 1;
		end
		
		if(i3 == (p3>>1))
		begin
			ClkOut1Hz <= 1'b1;
		end
		else if(i3 == p3)
		begin
			ClkOut1Hz <= 1'b0;
			i3 <= 1;
		end	
		
		if(i4 == (p4>>1))
		begin
			ClkOutLow <= 1'b1;
		end
		else if(i4 == p4)
		begin
			ClkOutLow <= 1'b0;
			i4 <= 1;
		end		
		
		if(i5 == (p5>>1))
		begin
			ClkOutHigh <= 1'b1;
		end
		else if(i5 == p5)
		begin
			ClkOutHigh <= 1'b0;
			i5 <= 1;
		end	
		
		if(i6 == (p6>>1))
		begin
			ClkOut4Hz <= 1'b1;
		end
		else if(i6 == p6)
		begin
			ClkOut4Hz <= 1'b0;
			i6 <= 1;
		end		
		
		if(i7 == (p7>>1))
		begin
			ClkOutMid <= 1'b1;
		end
		else if(i7 == p7)
		begin
			ClkOutMid <= 1'b0;
			i7 <= 1;
		end		
	end	
endmodule