keystates1.v

基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计&

// KeyStates.v	 		键盘状态切换模块		2006-11-3		version:1.0		作者：田世坤
//输入：
//		
//		
//输出：

module KeyStates(ClkIn, Reset, KeyIn, 
					StateOut);
input ClkIn, Reset;
input [7:0]KeyIn;
output [11:0]StateOut;
wire [11:0]StateOut;
//reg  StateOut[11:0];

reg [11:0] CurrentState, NextStateD, NextStateS, NextStateOK;

assign StateOut = CurrentState;

parameter ST = 12'b1110_00000000, STset7 = 12'b1110_10000000, STset6 = 12'b1110_01000000, STset4 = 12'b1110_00010000, STset3 = 12'b1110_00001000, STset1 = 12'b1110_00000010, STset0 = 12'b1110_00000001;
parameter SD = 12'b1101_00010100, SDset5 = 12'b1101_00100000, SDset4 = 12'b1101_00010000, SDset3 = 12'b1101_00001000, SDset2 = 12'b1101_00000100, SDset1 = 12'b1101_00000010, SDset0 = 12'b1101_00000001;
parameter SA = 12'b1101_00000000, SAset4 = 12'b1011_00010000, SAset3 = 12'b1101_00001000, SAset1 = 12'b1101_00000010, SAset0 = 12'b1101_00000001;
parameter SSW =  12'b0111_00000000, SSWRun =  12'b0111_00000100, SSWPause =  12'b0111_00000001;

always @(posedge ClkIn)
begin
	if(!Reset)
		begin
			CurrentState <= ST;
		end
	else
		begin
			case(KeyIn)
				8'b01111110:	CurrentState <= NextStateD;		//键0：显示状态切换
				8'b01111101:	CurrentState <= NextStateS;		//键1：设置状态切换
				8'b01111011:	CurrentState <= NextStateOK;	//键2：确定状态切换
				8'b10111110:	CurrentState <= SSW;			//键4：状态切换到秒表，并清零
				8'b10111101:	CurrentState <= SSWRun;			//键5：秒表状态切换到运行状态
				8'b10111011:	CurrentState <= SSWPause;		//键6：秒表状态切换到暂停状态
				default:		CurrentState <= CurrentState;
			endcase
		end
end

always @ (CurrentState)
begin
	case(CurrentState)
		
		/////////////////////////以下为时间状态变化///////////////////////////////
		ST:
			begin
				NextStateD = SD;
				NextStateS = STset7;
				NextStateOK = ST;
			end
		STset7:
			begin
				NextStateD = SD;
				NextStateS = STset6;
				NextStateOK = ST;
			end
		STset6:
			begin
				NextStateD = SD;
				NextStateS = STset4;
				NextStateOK = ST;
			end
		STset4:
			begin
				NextStateD = SD;
				NextStateS = STset3;
				NextStateOK = ST;
			end
		STset3:
			begin
				NextStateD = SD;
				NextStateS = STset1;
				NextStateOK = ST;
			end
		STset1:
			begin
				NextStateD = SD;
				NextStateS = STset0;
				NextStateOK = ST;
			end
		STset0:
			begin
				NextStateD = SD;
				NextStateS = STset7;
				NextStateOK = ST;
			end
		
		
		/////////////////////////以下为日期状态变化///////////////////////////////	
		SD:
			begin
				NextStateD = SA;
				NextStateS = SDset5;
				NextStateOK = SD;
			end
		SDset5:
			begin
				NextStateD = SA;
				NextStateS = SDset4;
				NextStateOK = SD;
			end	
		SDset4:
			begin
				NextStateD = SA;
				NextStateS = SDset3;
				NextStateOK = SD;
			end
		SDset3:
			begin
				NextStateD = SA;
				NextStateS = SDset2;
				NextStateOK = SD;
			end
		SDset2:
			begin
				NextStateD = SA;
				NextStateS = SDset1;
				NextStateOK = SD;
			end
		SDset1:
			begin
				NextStateD = SA;
				NextStateS = SDset0;
				NextStateOK = SD;
			end
		SDset0:
			begin
				NextStateD = SA;
				NextStateS = SDset5;
				NextStateOK = SD;
			end
			
			
		/////////////////////////以下为闹钟状态变化///////////////////////////////
		SA:
			begin
				NextStateD = SSW;
				NextStateS = SAset4;
				NextStateOK = SA;
			end
		SAset4:
			begin
				NextStateD = SSW;
				NextStateS = SAset3;
				NextStateOK = SA;
			end
		SAset3:
			begin
				NextStateD = SSW;
				NextStateS = SAset1;
				NextStateOK = SA;
			end
		SAset1:
			begin
				NextStateD = SSW;
				NextStateS = SAset0;
				NextStateOK = SA;
			end
		SAset0:
			begin
				NextStateD = SSW;
				NextStateS = SAset4;
				NextStateOK = SA;
			end
			
		/////////////////////////以下为秒表状态变化///////////////////////////////	
		SSW:
			begin
				NextStateD = ST;
			end	
		SSWRun:
			begin
				NextStateD = ST;
			end	
		SSWPause:
			begin
				NextStateD = ST;
			end	
			
		default:
			begin
				NextStateD = SD;
				NextStateS = STset7;
				NextStateOK = ST;
			end
	endcase
end

endmodule