alarm.v

基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计&

// Alarm.v	 		闹钟模块		2006-11-3		version:1.0		作者：田世坤
//输入：
//		
//		
//输出：

module Alarm(ClkIn, Reset, KeyIn, State, AlarmEn, D7, D6, D5, D4, D3, D2, D1, D0,  
			DA7, DA6, DA5, DA4, DA3, DA2, DA1, DA0, AlarmOut);
input ClkIn, Reset, AlarmEn;
input [3:0] D7, D6, D5, D4, D3, D2, D1, D0;
input [7:0]KeyIn;
input [11:0] State;
output AlarmOut;
reg AlarmOut;
output [3:0]DA4, DA3, DA1, DA0;
reg  [3:0] DA4, DA3, DA1, DA0;
output [3:0] DA7, DA6, DA5,DA2;
  
assign DA2 = 4'ha;					
assign DA5 = 4'ha;
assign DA6 = 4'hd;
assign DA7 = 4'ha;

parameter SAset4 = 12'b1011_00010000, SAset3 = 12'b1011_00001000, SAset1 = 12'b1011_00000010, SAset0 = 12'b1011_00000001;

always @(posedge ClkIn or negedge Reset)
begin
	if(!Reset)
		begin
			DA0 = 4'h0;
			DA1 = 4'h0;
			DA3 = 4'h7;
			DA4 = 4'h0;
			AlarmOut = 1'b0;
		end
	else
		begin				//时、分判断
			
			if(DA0 > 4'h9)
			begin
				DA0 = 4'h0;
				DA1 = DA1 + 4'h1;
			end
			if(DA1 > 4'h5)
			begin
				DA1 = 4'h0;
				DA3 = DA3 + 4'h1;
			end
			if(DA3 > 4'h9)
			begin
				DA3 = 4'h0;
				DA4 = DA4 + 4'h1;
			end
			if({DA4,DA3} > 8'h23)
			begin
				DA4 = 4'h0;
				DA3 = 4'h0;
			end
								
			if(D7==DA4 && D6==DA3 && D4==DA1 && D3==DA0 && AlarmEn)
			begin	
				AlarmOut = 1'b1;
			end
			else
			begin
				AlarmOut = 1'b0;
			end
					
			case(State)
				SAset4 | {4'b0000, AlarmEn, 7'b0000000}:
					begin
						if(KeyIn == 8'b01110111)
							DA4 = DA4 + 4'h1;
					end
					
				SAset3 | {4'b0000, AlarmEn, 7'b0000000}:
					begin
						if(KeyIn == 8'b01110111)
							DA3 = DA3 + 4'h1;
					end
					
				SAset1 | {4'b0000, AlarmEn, 7'b0000000}:
					begin
						if(KeyIn == 8'b01110111)
							DA1 = DA1 + 4'h1;
					end
					
				SAset0 | {4'b0000, AlarmEn, 7'b0000000}:
					begin
						if(KeyIn == 8'b01110111)
							DA0 = DA0 + 4'h1;
					end
					
				default:
					begin
					
					end
			endcase
		end
	
end

endmodule