keystates.v

基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计&

// KeyStates.v	 		键盘状态切换模块		2006-11-3		version:1.0		作者：田世坤
//输入：
//		
//		
//输出：

module KeyStates(ClkIn, Reset, KeyIn,  
					AlarmEn, StateOut);
input ClkIn, Reset;
input [7:0]KeyIn;
output AlarmEn;
reg AlarmEn;
output [11:0]StateOut;
wire [11:0]StateOut;
//reg  StateOut[11:0];

reg [11:0] CurrentState, NextStateD, NextStateS, NextStateOK, NextStateAL, OutTemp;

assign StateOut = OutTemp;

parameter ST = 12'b1110_00000000, STset7 = 12'b1110_10000000, STset6 = 12'b1110_01000000, STset4 = 12'b1110_00010000, STset3 = 12'b1110_00001000, STset1 = 12'b1110_00000010, STset0 = 12'b1110_00000001;
parameter SD = 12'b1101_00010100, SDset5 = 12'b1101_00100000, SDset4 = 12'b1101_00010000, SDset3 = 12'b1101_00001000, SDset2 = 12'b1101_00000100, SDset1 = 12'b1101_00000010, SDset0 = 12'b1101_00000001;
parameter SA = 12'b1011_00000000, SAset4 = 12'b1011_00010000, SAset3 = 12'b1011_00001000, SAset1 = 12'b1011_00000010, SAset0 = 12'b1011_00000001;
parameter SSW =  12'b0111_00000000, SSWRun =  12'b0111_00000100, SSWPause =  12'b0111_00000001;

always @(posedge ClkIn or negedge Reset)
begin
	if(!Reset)
		begin
			CurrentState <= ST;
			AlarmEn <= 1'b1;
		end
	else
		begin
			case(KeyIn)
				8'b01111110:	CurrentState <= NextStateD;		//键0：显示状态切换
				8'b01111101:	CurrentState <= NextStateS;		//键1：设置状态切换
				8'b01111011:	CurrentState <= NextStateOK;	//键2：确定状态切换
				8'b10111110:	CurrentState <= SSW;			//键4：状态切换到秒表，并清零
				8'b10111101:	CurrentState <= SSWRun;			//键5：秒表状态切换到运行状态
				8'b10111011:	CurrentState <= SSWPause;		//键6：秒表状态切换到暂停状态
				8'b10110111:	AlarmEn <= ~AlarmEn;			//键7：闹钟使能状态切换
				default:		CurrentState <= CurrentState;
			endcase


		case(CurrentState[11:8])
			ST[11:8]:
				begin
					NextStateD = SD;
					NextStateOK = ST;
					case(CurrentState[7:0])
						ST[7:0]:		NextStateS = STset7;
						STset7[7:0]:	NextStateS = STset6;
						STset6[7:0]:	NextStateS = STset4;
						STset4[7:0]:	NextStateS = STset3;
						STset3[7:0]:	NextStateS = STset1;
						STset1[7:0]:	NextStateS = STset0;
						STset0[7:0]:	NextStateS = STset7;
						default:		NextStateS = STset7;
					endcase
				end
			
			SD[11:8]:
				begin
					NextStateD = SA;
					NextStateOK = SD;
					case(CurrentState[7:0])
						SD[7:0]:		NextStateS = SDset5;
						SDset5[7:0]:	NextStateS = SDset4;
						SDset4[7:0]:	NextStateS = SDset3;
						SDset3[7:0]:	NextStateS = SDset2;
						SDset2[7:0]:	NextStateS = SDset1;
						SDset1[7:0]:	NextStateS = SDset0;
						SDset0[7:0]:	NextStateS = SDset5;
						default:		NextStateS = SDset5;
					endcase
				end
			
			SA[11:8]:
				begin
					NextStateD = SSW;
					NextStateOK = SA;
					case(CurrentState[7:0])
						SA[7:0]:		NextStateS = SAset4;
						SAset4[7:0]:	NextStateS = SAset3;
						SAset3[7:0]:	NextStateS = SAset1;
						SAset1[7:0]:	NextStateS = SAset0;
						SAset0[7:0]:	NextStateS = SAset4;
						default:		NextStateS = SAset4;
					endcase
				end
				
			SSW[11:8]:
				begin
					NextStateD = ST;
				end
			
			default:	
				begin
					NextStateS = STset7;
					NextStateD = SD;
					NextStateOK = ST;
				end
		endcase
		
		if(CurrentState[11:8] == SA[11:8])
			OutTemp = CurrentState | {4'b0000, AlarmEn, 7'b0000};
		else
			OutTemp = CurrentState;
			
	end
end

endmodule