pd0.v

来自「数字边沿鉴相器 verilog源程序」· Verilog 代码 · 共 30 行

module pd0 ( In_0 , In_1 , Out_0 , Out_1 ) ;

input  In_0 ,  In_1 ;
output Out_0 , Out_1 ;

wire   T_In_0 ,T_In_1 ;
wire   T_F0_0 ,T_F0_1 , T_F1_0 , T_F1_1 ;
wire   T_U ;


assign T_In_0 = ~ ( In_0 & Out_1 ) ;
assign T_In_1 = ~ ( In_1 & Out_0 ) ;


assign T_F0_0 = ~ ( T_In_0 & T_F0_1 ) ;
assign T_F0_1 = ~ ( T_U    & T_F0_0 ) ;


assign T_F1_0 = ~ ( T_In_1 & T_F1_1 ) ;
assign T_F1_1 = ~ ( T_U    & T_F1_0 ) ;


assign T_U = ~ ( T_In_0 & T_In_1 & T_F0_0 & T_F1_0) ;


assign Out_0 = ~ ( T_In_0 & T_F0_0 & T_U ) ;
assign Out_1 = ~ ( T_In_1 & T_F1_0 & T_U ) ;


endmodule