leg_soc_tb.v

verilog hdl编写,六段流水线CPU.程序完整

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  LEG cpu core                                               ////
////                                                             ////
////  This file is part of the LEG FPGA SOC project              ////
////                                                             ////
////                                                             ////
////  To Do:                                                     ////
////   - make it smaller and faster                              ////
////   - rewrite the register file and data path                 ////
////  Author(s):                                                 ////
////      - Alex Li, [e-mail]                      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Li datou                            ////
////                         [e-mail]              ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// ARM, the ARM Powered logo, Thumb, and StrongARM are         ////
//// registerd trademarks of ARM Limited, this core is simply    ////
//// build for fun, please do not use for commerical propose     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Date of Creation: 2006.11.28                                ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
////  Description                                                ////
////  leg FPGA SOC testbench.                                    ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
`include "leg_define.v"
module leg_soc_tb;
reg             clk;
reg             rst;

initial
begin
#0        clk =0;
          #10  forever   #10 clk = ~clk;
end

initial
begin
        rst =0;
          #10 rst = 1;
          #100 rst = 0;
          #500_0000 $stop;
end

wire            sdram_clk;
wire            flash_clk;
wire    [3:0]   ncs;
wire            nwe;
wire            ncas;
wire            nras;
wire    [3:0]   dqm;
wire    [3:0]   sdram_bank_sel; //
wire    [23:0]  mem_addr;
wire    [31:0]  mem_data;

leg_soc soc_top(
        //memory interface, duplex by sdram and flash        
        .sdram_clk(sdram_clk),
        .flash_clk(flash_clk),
        .ncs(ncs),
        .nwe(nwe),
        .ncas(ncas),
        .nras(nras),
        .dqm(dqm),
        .sdram_bank_sel(sdram_bank_sel),
        .mem_addr(mem_addr),
        .mem_data(mem_data),
        //uart if
        
        //external interrupt if
        
        //A/D if
        
        //D/A if
        
        //I2C bus if
        
        //system clock and rst
        .clk(clk),
        .rst(rst)
        );



endmodule