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📄 leg_rf.v

📁 verilog hdl编写,六段流水线CPU.程序完整
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                                case(raddrc)
                                5'd00 : rdatac_r <= mem_content00;
                                5'd01 : rdatac_r <= mem_content01;
                                5'd02 : rdatac_r <= mem_content02;
                                5'd03 : rdatac_r <= mem_content03;
                                5'd04 : rdatac_r <= mem_content04;
                                5'd05 : rdatac_r <= mem_content05;
                                5'd06 : rdatac_r <= mem_content06;
                                5'd07 : rdatac_r <= mem_content07;
                                5'd08 : rdatac_r <= mem_content08;
                                5'd09 : rdatac_r <= mem_content09;
                                5'd10 : rdatac_r <= mem_content10;
                                5'd11 : rdatac_r <= mem_content11;
                                5'd12 : rdatac_r <= mem_content12;
                                5'd13 : rdatac_r <= mem_content13;
                                5'd14 : rdatac_r <= mem_content14;
                                5'd15 : rdatac_r <= mem_content15;
                                5'd16 : rdatac_r <= mem_content16;
                                5'd17 : rdatac_r <= mem_content17;
                                5'd18 : rdatac_r <= mem_content18;
                                5'd19 : rdatac_r <= mem_content19;
                                5'd20 : rdatac_r <= mem_content20;
                                5'd21 : rdatac_r <= mem_content21;
                                5'd22 : rdatac_r <= mem_content22;
                                5'd23 : rdatac_r <= mem_content23;
                                5'd24 : rdatac_r <= mem_content24;
                                5'd25 : rdatac_r <= mem_content25;
                                5'd26 : rdatac_r <= mem_content26;
                                5'd27 : rdatac_r <= mem_content27;
                                5'd28 : rdatac_r <= mem_content28;
                                5'd29 : rdatac_r <= mem_content29;
                                5'd30 : rdatac_r <= mem_content30;
                                5'd31 : rdatac_r <= mem_content31;
                                endcase  
                        end
                end
        end
        //------------------------------------------------data write in
        //port a has higher priority than port b
        always@(posedge clk or posedge rst)
        begin
               if (rst) begin
                        mem_content00 <= 32'hffffffff;  //for test only
                        mem_content01 <= 32'h00000a44;  //for test only
                        mem_content02 <= 32'h0;
                        mem_content03 <= 32'h0;
                        mem_content04 <= 32'h0;
                        mem_content05 <= 32'h0;
                        mem_content06 <= 32'h0;
                        mem_content07 <= 32'h0;
                        mem_content08 <= 32'h0;
                        mem_content09 <= 32'h0;
                        mem_content10 <= 32'h0;
                        mem_content11 <= 32'h0;
                        mem_content12 <= 32'h0;
                        mem_content13 <= 32'h00000a00;  //for test only
                        mem_content14 <= 32'h00000004;  //for test only
                        mem_content15 <= 32'h0;
                        mem_content16 <= 32'h0;
                        mem_content17 <= 32'h0;
                        mem_content18 <= 32'h0;
                        mem_content19 <= 32'h0;
                        mem_content20 <= 32'h0;
                        mem_content21 <= 32'h0;
                        mem_content22 <= 32'h0;
                        mem_content23 <= 32'h0;
                        mem_content24 <= 32'h0;
                        mem_content25 <= 32'h0;
                        mem_content26 <= 32'h0;
                        mem_content27 <= 32'h0;
                        mem_content28 <= 32'h0;
                        mem_content29 <= 32'h0;
                        mem_content30 <= 32'h0;
                        mem_content31 <= 32'h0;
                        
               end
               else begin
                        if (waddra == 5'd00 && wea) mem_content00 <= wdataa; else if (waddrb == 5'd00 && web) mem_content00 <= wdatab;
                        if (waddra == 5'd01 && wea) mem_content01 <= wdataa; else if (waddrb == 5'd01 && web) mem_content01 <= wdatab;
                        if (waddra == 5'd02 && wea) mem_content02 <= wdataa; else if (waddrb == 5'd02 && web) mem_content02 <= wdatab;
                        if (waddra == 5'd03 && wea) mem_content03 <= wdataa; else if (waddrb == 5'd03 && web) mem_content03 <= wdatab;
                        if (waddra == 5'd04 && wea) mem_content04 <= wdataa; else if (waddrb == 5'd04 && web) mem_content04 <= wdatab;
                        if (waddra == 5'd05 && wea) mem_content05 <= wdataa; else if (waddrb == 5'd05 && web) mem_content05 <= wdatab;
                        if (waddra == 5'd06 && wea) mem_content06 <= wdataa; else if (waddrb == 5'd06 && web) mem_content06 <= wdatab;
                        if (waddra == 5'd07 && wea) mem_content07 <= wdataa; else if (waddrb == 5'd07 && web) mem_content07 <= wdatab;
                        if (waddra == 5'd08 && wea) mem_content08 <= wdataa; else if (waddrb == 5'd08 && web) mem_content08 <= wdatab;
                        if (waddra == 5'd09 && wea) mem_content09 <= wdataa; else if (waddrb == 5'd09 && web) mem_content09 <= wdatab;
                        if (waddra == 5'd10 && wea) mem_content10 <= wdataa; else if (waddrb == 5'd10 && web) mem_content10 <= wdatab;
                        if (waddra == 5'd11 && wea) mem_content11 <= wdataa; else if (waddrb == 5'd11 && web) mem_content11 <= wdatab;
                        if (waddra == 5'd12 && wea) mem_content12 <= wdataa; else if (waddrb == 5'd12 && web) mem_content12 <= wdatab;
                        if (waddra == 5'd13 && wea) mem_content13 <= wdataa; else if (waddrb == 5'd13 && web) mem_content13 <= wdatab;
                        if (waddra == 5'd14 && wea) mem_content14 <= wdataa; else if (waddrb == 5'd14 && web) mem_content14 <= wdatab;
                        if (waddra == 5'd15 && wea) mem_content15 <= wdataa; else if (waddrb == 5'd15 && web) mem_content15 <= wdatab;
                        if (waddra == 5'd16 && wea) mem_content16 <= wdataa; else if (waddrb == 5'd16 && web) mem_content16 <= wdatab;
                        if (waddra == 5'd17 && wea) mem_content17 <= wdataa; else if (waddrb == 5'd17 && web) mem_content17 <= wdatab;
                        if (waddra == 5'd18 && wea) mem_content18 <= wdataa; else if (waddrb == 5'd18 && web) mem_content18 <= wdatab;
                        if (waddra == 5'd19 && wea) mem_content19 <= wdataa; else if (waddrb == 5'd19 && web) mem_content19 <= wdatab;
                        if (waddra == 5'd20 && wea) mem_content20 <= wdataa; else if (waddrb == 5'd20 && web) mem_content20 <= wdatab;
                        if (waddra == 5'd21 && wea) mem_content21 <= wdataa; else if (waddrb == 5'd21 && web) mem_content21 <= wdatab;
                        if (waddra == 5'd22 && wea) mem_content22 <= wdataa; else if (waddrb == 5'd22 && web) mem_content22 <= wdatab;
                        if (waddra == 5'd23 && wea) mem_content23 <= wdataa; else if (waddrb == 5'd23 && web) mem_content23 <= wdatab;
                        if (waddra == 5'd24 && wea) mem_content24 <= wdataa; else if (waddrb == 5'd24 && web) mem_content24 <= wdatab;
                        if (waddra == 5'd25 && wea) mem_content25 <= wdataa; else if (waddrb == 5'd25 && web) mem_content25 <= wdatab;
                        if (waddra == 5'd26 && wea) mem_content26 <= wdataa; else if (waddrb == 5'd26 && web) mem_content26 <= wdatab;
                        if (waddra == 5'd27 && wea) mem_content27 <= wdataa; else if (waddrb == 5'd27 && web) mem_content27 <= wdatab;
                        if (waddra == 5'd28 && wea) mem_content28 <= wdataa; else if (waddrb == 5'd28 && web) mem_content28 <= wdatab;
                        if (waddra == 5'd29 && wea) mem_content29 <= wdataa; else if (waddrb == 5'd29 && web) mem_content29 <= wdatab;
                        if (waddra == 5'd30 && wea) mem_content30 <= wdataa; else if (waddrb == 5'd30 && web) mem_content30 <= wdatab;
                        if (waddra == 5'd31 && wea) mem_content31 <= wdataa; else if (waddrb == 5'd31 && web) mem_content31 <= wdatab;
               end
        end

        //-------------------------------------------------------------------
        //foward path from alu or load data
        //write port A has priority over port B
        always@(posedge clk or posedge rst)
        begin
                if (rst) begin
                        d_addra_d <= 5'b0;
                end
                else begin
                        if (d_en)
                                d_addra_d <= raddra;
                end
        end
        
        always@(posedge clk or posedge rst)
        begin
                if (rst) begin
                        d_addrb_d <= 5'b0;
                end
                else begin
                        if (d_en)
                                d_addrb_d <= raddrb;
                end
        end
        
        always@(posedge clk or posedge rst)
        begin
                if (rst) begin
                        d_addrc_d <= 5'b0;
                end
                else begin
                        if (d_en)
                                d_addrc_d <= raddrc;
                end
        end
        //---------------------------------------------------------------------
        //WRITE THROUGH OPREATION
        always@(posedge clk or posedge rst)
        begin
                if (rst)
                        rdataa_temp <= 32'h0;
                else begin
                        if (d_en) begin
                                if (raddra == waddra && wea) begin
                                        rdataa_temp <= wdataa;
                                end
                                else if (raddra == waddrb && web) begin 
                                        rdataa_temp <= wdatab;
                                end
                        end
                end
        end       
        always@(posedge clk or posedge rst)
        begin
                if (rst)
                        rdatab_temp <= 32'h0;
                else begin    
                        if (d_en) begin
                                if (raddrb == waddra && wea) begin
                                        rdatab_temp <= wdataa;
                                end
                                else if (raddrb == waddrb && web) begin 
                                        rdatab_temp <= wdatab;
                                end
                        end
                end
        end         
        always@(posedge clk or posedge rst)
        begin
                if (rst)
                        rdatac_temp <= 32'h0;
                else begin     
                        if (d_en) begin
                                if (raddrc == waddra && wea) begin
                                        rdatac_temp <= wdataa;
                                end
                                else if (raddrc == waddrb && web) begin 
                                        rdatac_temp <= wdatab;
                                end
                        end
                end
        end     
        always@(posedge clk or posedge rst)
        begin
                if (rst) begin
                        waddra_d <= 5'b0;
                        waddrb_d <= 5'b0;
                        wea_d    <= 1'b0;
                        web_d    <= 1'b0;
                end
                else begin 
                        if (d_en) begin
                                waddra_d <= waddra;
                                waddrb_d <= waddrb;
                                wea_d    <= wea;
                                web_d    <= web;
                        end
                end
        end
        
        always@(posedge clk or posedge rst)
        begin
                if (rst) begin
                        a_foward_temp_ena <= 1'b0;
                        w_foward_temp_ena <= 1'b0;
                end
                else begin  
                        if (d_en) begin
                                if (raddrc == waddra && wea) begin
                                        a_foward_temp_ena <= 1'b1;
                                end
                                else if (raddrc == waddrb && web) begin 
                                        w_foward_temp_ena <= 1'b1;
                                end
                                else begin
                                        a_foward_temp_ena <= 1'b0;
                                        w_foward_temp_ena <= 1'b0;
                                end 
                        end
                end
        end     
        //------------------------------output selection
        assign  rdataa = (waddra == d_addra_d && wea) ? wdataa : (waddrb == d_addra_d && web) ? wdatab : ((waddra_d == d_addra_d && wea_d) || (waddrb_d == d_addra_d && web_d))? rdataa_temp : rdataa_r;
        assign  rdatab = (waddra == d_addrb_d && wea) ? wdataa : (waddrb == d_addrb_d && web) ? wdatab : ((waddra_d == d_addrb_d && wea_d) || (waddrb_d == d_addrb_d && web_d))? rdatab_temp : rdatab_r;
        assign  rdatac = (a_foward_ena && wea) ? wdataa : (w_foward_ena && web) ? wdatab : ((a_foward_temp_ena && wea_d) || (w_foward_temp_ena && web_d))? rdatac_temp : rdatac_r;
        //-----------------------------------------------------------------------
        //debug info 
        //`ifdef DEBUG_INFO
        //        //synopsis translate off
        //        always@(posedge clk)
        //        begin   
        //                if (wea && web && waddra == waddrb)
        //                        $display("%d : warning--- two waddr conflict  at %h", $time, waddra);
        //                if (wea)
        //                        $display("%d : info------ now write  %h  to %h from port a", $time, wdataa, waddra);
        //                if (web)
        //                        $display("%d : info------ now write  %h  to %h from port b", $time, wdatab, waddrb);
        //        end
        //        //synopsis translate on
        //`endif
`endif

endmodule

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