📄 leg_rf.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// LEG cpu core ////
//// ////
//// This file is part of the LEG FPGA SOC project ////
//// ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// - rewrite the register file and data path ////
//// Author(s): ////
//// - Alex Li, Alexli8055@hotmail.com ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Li datou ////
//// Alexli8055@hotmail.com ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// ARM, the ARM Powered logo, Thumb, and StrongARM are ////
//// registerd trademarks of ARM Limited, this core is simply ////
//// build for fun, please do not use for commerical propose ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Date of Creation: 2006.11.28 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description ////
//// leg core register file module. ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "leg_define.v"
module leg_rf(
//3 read port
raddra,
raddrb,
raddrc,
rdataa,
rdatab,
rdatac,
//2 write port
waddra,
waddrb,
wdataa,
wdatab,
a_foward_ena,
w_foward_ena,
wea,
web,
d_en,
//system if
clk,
rst
);
input [4:0] raddra;
input [4:0] raddrb;
input [4:0] raddrc;
output [31:0] rdataa;
output [31:0] rdatab;
output [31:0] rdatac;
input [4:0] waddra;
input [4:0] waddrb;
input [31:0] wdataa;
input [31:0] wdatab;
input wea;
input web;
input clk;
input rst;
input a_foward_ena;
input w_foward_ena;
input d_en;
`ifdef ALTERA_CYCLONE
always@(posedge clk)
$display("you 'd better use the actel 's arm7 core!");
`else
//simulation only
wire [31:0] rdataa;
wire [31:0] rdatab;
wire [31:0] rdatac;
reg [31:0] rdataa_r;
reg [31:0] rdatab_r;
reg [31:0] rdatac_r;
reg [4:0] d_addra_d;
reg [4:0] d_addrb_d;
reg [4:0] d_addrc_d;
reg [31:0] rdataa_temp;
reg [31:0] rdatab_temp;
reg [31:0] rdatac_temp;
reg [4:0] waddra_d;
reg [4:0] waddrb_d;
reg wea_d;
reg web_d;
reg a_foward_temp_ena;
reg w_foward_temp_ena;
reg [31:0] mem_content00;
reg [31:0] mem_content01;
reg [31:0] mem_content02;
reg [31:0] mem_content03;
reg [31:0] mem_content04;
reg [31:0] mem_content05;
reg [31:0] mem_content06;
reg [31:0] mem_content07;
reg [31:0] mem_content08;
reg [31:0] mem_content09;
reg [31:0] mem_content10;
reg [31:0] mem_content11;
reg [31:0] mem_content12;
reg [31:0] mem_content13;
reg [31:0] mem_content14;
reg [31:0] mem_content15;
reg [31:0] mem_content16;
reg [31:0] mem_content17;
reg [31:0] mem_content18;
reg [31:0] mem_content19;
reg [31:0] mem_content20;
reg [31:0] mem_content21;
reg [31:0] mem_content22;
reg [31:0] mem_content23;
reg [31:0] mem_content24;
reg [31:0] mem_content25;
reg [31:0] mem_content26;
reg [31:0] mem_content27;
reg [31:0] mem_content28;
reg [31:0] mem_content29;
reg [31:0] mem_content30;
reg [31:0] mem_content31;
//-----------------------memory contents
//a port read data
always@(posedge clk or posedge rst)
begin
if (rst) begin
rdataa_r <= 32'h0;
end
else begin
if (d_en) begin
case(raddra)
5'd00 : rdataa_r <= mem_content00;
5'd01 : rdataa_r <= mem_content01;
5'd02 : rdataa_r <= mem_content02;
5'd03 : rdataa_r <= mem_content03;
5'd04 : rdataa_r <= mem_content04;
5'd05 : rdataa_r <= mem_content05;
5'd06 : rdataa_r <= mem_content06;
5'd07 : rdataa_r <= mem_content07;
5'd08 : rdataa_r <= mem_content08;
5'd09 : rdataa_r <= mem_content09;
5'd10 : rdataa_r <= mem_content10;
5'd11 : rdataa_r <= mem_content11;
5'd12 : rdataa_r <= mem_content12;
5'd13 : rdataa_r <= mem_content13;
5'd14 : rdataa_r <= mem_content14;
5'd15 : rdataa_r <= mem_content15;
5'd16 : rdataa_r <= mem_content16;
5'd17 : rdataa_r <= mem_content17;
5'd18 : rdataa_r <= mem_content18;
5'd19 : rdataa_r <= mem_content19;
5'd20 : rdataa_r <= mem_content20;
5'd21 : rdataa_r <= mem_content21;
5'd22 : rdataa_r <= mem_content22;
5'd23 : rdataa_r <= mem_content23;
5'd24 : rdataa_r <= mem_content24;
5'd25 : rdataa_r <= mem_content25;
5'd26 : rdataa_r <= mem_content26;
5'd27 : rdataa_r <= mem_content27;
5'd28 : rdataa_r <= mem_content28;
5'd29 : rdataa_r <= mem_content29;
5'd30 : rdataa_r <= mem_content30;
5'd31 : rdataa_r <= mem_content31;
endcase
end
end
end
//b port read data
always@(posedge clk or posedge rst)
begin
if (rst) begin
rdatab_r <= 32'h0;
end
else begin
if (d_en) begin
case(raddrb)
5'd00 : rdatab_r <= mem_content00;
5'd01 : rdatab_r <= mem_content01;
5'd02 : rdatab_r <= mem_content02;
5'd03 : rdatab_r <= mem_content03;
5'd04 : rdatab_r <= mem_content04;
5'd05 : rdatab_r <= mem_content05;
5'd06 : rdatab_r <= mem_content06;
5'd07 : rdatab_r <= mem_content07;
5'd08 : rdatab_r <= mem_content08;
5'd09 : rdatab_r <= mem_content09;
5'd10 : rdatab_r <= mem_content10;
5'd11 : rdatab_r <= mem_content11;
5'd12 : rdatab_r <= mem_content12;
5'd13 : rdatab_r <= mem_content13;
5'd14 : rdatab_r <= mem_content14;
5'd15 : rdatab_r <= mem_content15;
5'd16 : rdatab_r <= mem_content16;
5'd17 : rdatab_r <= mem_content17;
5'd18 : rdatab_r <= mem_content18;
5'd19 : rdatab_r <= mem_content19;
5'd20 : rdatab_r <= mem_content20;
5'd21 : rdatab_r <= mem_content21;
5'd22 : rdatab_r <= mem_content22;
5'd23 : rdatab_r <= mem_content23;
5'd24 : rdatab_r <= mem_content24;
5'd25 : rdatab_r <= mem_content25;
5'd26 : rdatab_r <= mem_content26;
5'd27 : rdatab_r <= mem_content27;
5'd28 : rdatab_r <= mem_content28;
5'd29 : rdatab_r <= mem_content29;
5'd30 : rdatab_r <= mem_content30;
5'd31 : rdatab_r <= mem_content31;
endcase
end
end
end
//b port read data
always@(posedge clk or posedge rst)
begin
if (rst) begin
rdatac_r <= 32'h0;
end
else begin
if (d_en) begin
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