leg_mem_arbitor.v

verilog hdl编写,六段流水线CPU.程序完整

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  LEG cpu core                                               ////
////                                                             ////
////  This file is part of the LEG FPGA SOC project              ////
////                                                             ////
////                                                             ////
////  To Do:                                                     ////
////   - make it smaller and faster                              ////
////   - rewrite the register file and data path                 ////
////  Author(s):                                                 ////
////      - Alex Li, [e-mail]                      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Li datou                            ////
////                         [e-mail]              ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// ARM, the ARM Powered logo, Thumb, and StrongARM are         ////
//// registerd trademarks of ARM Limited, this core is simply    ////
//// build for fun, please do not use for commerical propose     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Date of Creation: 2006.11.28                                ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
////  Description                                                ////
////  leg core memory interface, now only a dummy module for     ////
////  simulation.                                                ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
`include "leg_define.v"
module leg_mem_arbitor(
        //i_cache if
        ic_adr_i,
        ic_dat_o,
        ic_stb_i,
        ic_cyc_i,
        ic_ack_o,
        ic_sel_i,
        ic_tgd_o,
        ic_tgd_i,

        //d_cache if
        dc_adr_i,
        dc_dat_o,
        dc_dat_i,
        dc_stb_i,
        dc_cyc_i,
        dc_ack_o,
        dc_sel_i,
        dc_tgd_o,
        dc_tgd_i,
        dc_we_i,

        //none cacheable data to core
        d_address,
        d_wait,
        d_re,
        d_we,
        d_datain,
        d_dataout,
        d_be,
        //to sdram controller
        //to flash controller
        //to slow peripheral
        //system clock
        clk,
        rst
        );
        
input           clk;
input           rst;

input   [31:0]  ic_adr_i;
output  [31:0]  ic_dat_o;
input           ic_stb_i;
input           ic_cyc_i;
output          ic_ack_o;
input   [3:0]   ic_sel_i;
output  [3:0]   ic_tgd_o;
input   [3:0]   ic_tgd_i;

input   [31:0]  dc_adr_i;
output  [31:0]  dc_dat_o;
input   [31:0]  dc_dat_i;
input           dc_stb_i;
input           dc_cyc_i;
output          dc_ack_o;
input   [3:0]   dc_sel_i;
output  [3:0]   dc_tgd_o;
input   [3:0]   dc_tgd_i;
input           dc_we_i;

input   [31:0]  d_address;
output  [31:0]  d_dataout;
output          d_wait;
input           d_re;
input           d_we;
input   [31:0]  d_datain;
input   [3:0]   d_be;

`ifdef DEBUG_INFO

//memory module for debug i cache and d cache

reg     [31:0]  mem [131071:0];
reg     [31:0]  i_data;
reg     [31:0]  d_data;
reg     [3:0]   i_tgd_o;
reg     [3:0]   d_tgd_o;


wire            d_read_from_dc;
assign          d_read_from_dc = (d_re || (dc_stb_i && !dc_we_i && dc_cyc_i))? 1'b1 : 1'b0;
assign          dc_dat_o = d_data;
assign          d_wait = 1'b0;
assign          d_dataout = d_data;
assign          ic_tgd_o = i_tgd_o;
assign          dc_tgd_o = d_tgd_o;
//dc read
always@(posedge clk or posedge rst)
begin
        if (rst) begin
                d_data <= 32'h0;
        end
        else begin
                if (d_read_from_dc) begin
                        d_data <= mem[dc_adr_i[31:02]-1];
                end
        end
end

always@(posedge clk or posedge rst)
begin
        if (rst) begin
                d_tgd_o <= 4'h0;
        end
        else begin
                d_tgd_o <= {4{d_read_from_dc}};
        end
end

wire            i_read_from_dc;
assign          i_read_from_dc = (ic_stb_i && ic_sel_i && ic_cyc_i)? 1'b1 : 1'b0;
assign          ic_dat_o = i_data;

//ic read
always@(posedge clk or posedge rst)
begin
        if (rst) begin
                i_data <= 32'h0;
        end
        else begin
                if (i_read_from_dc) begin
                        i_data <= mem[ic_adr_i[31:02]-1];
                end
        end
end

always@(posedge clk or posedge rst)
begin
        if (rst) begin
                i_tgd_o <= 4'h0;
        end
        else begin
                i_tgd_o <= {4{i_read_from_dc}};
        end
end

//dc write
wire            d_write_from_dc;
assign          d_write_from_dc = (d_we || (dc_stb_i && dc_we_i && dc_cyc_i))? 1'b1 : 1'b0;
wire    [31:0]  d_wdata_pre;
wire    [31:0]  d_wdata;
assign          d_wdata_pre = mem[d_address];

assign          d_wdata[07:00] = (d_we && d_be[0])? d_datain[07:00] : (d_write_from_dc && dc_sel_i[0]) ? dc_dat_i[07:00] : d_wdata_pre[07:00];
assign          d_wdata[15:08] = (d_we && d_be[1])? d_datain[15:08] : (d_write_from_dc && dc_sel_i[1]) ? dc_dat_i[15:08] : d_wdata_pre[15:08];
assign          d_wdata[23:16] = (d_we && d_be[2])? d_datain[23:16] : (d_write_from_dc && dc_sel_i[2]) ? dc_dat_i[23:16] : d_wdata_pre[23:16];
assign          d_wdata[31:24] = (d_we && d_be[3])? d_datain[31:24] : (d_write_from_dc && dc_sel_i[3]) ? dc_dat_i[31:24] : d_wdata_pre[31:24];

always@(posedge clk)
begin
        if (d_write_from_dc)
                mem[d_address] <= d_wdata;
end

//end simulation contents

//initial load data for simulation
 
initial begin
        $readmemh("inst_code.txt", mem);
end

`else   //real implementation

//the memory arbitor is a simplified implementation of wishbone arbitor
//d cache has a high priority than the i cache
//the memory access will be serialized for the sdram and flash controller
//the memory access will have a one cycle delay on both requrest and response side
//
wire    [31:0]  addr_from_core;
wire    [31:0]  data_from_core;
wire            re_from_core;
wire            we_from_core;

//dc if handling
wire            dc_re;
wire            dc_we;

assign          dc_re = (dc_stb_i && dc_cyc_i && !dc_we_i) ? 1'b1 : 1'b0;
assign          dc_we = (dc_stb_i && dc_cyc_i &&  dc_we_i) ? 1'b1 : 1'b0;
assign          ic_re = (ic_stb_i && ic_cyc_i) ? 1'b1 : 1'b0;

wire    
assign          addr_from_core = (d_re || d_we)? d_address :
                                 (dc_re || dc_we) ? dc_adr_i : 
                                 ic_adr_i;
   
//for ic, no data from it at all
assign          data_from_core = (d_we)? d_datain : dc_dat_i; 
                  
//read request queue
//implemented in the registers
reg     [3:0]   request_queue_mem [7:0];
reg     [2:0]   request_queue_waddr;
reg     [2:0]   request_queue_raddr;


`endif
endmodule