📄 leg_soc.v
字号:
/////////////////////////////////////////////////////////////////////
//// ////
//// LEG cpu core ////
//// ////
//// This file is part of the LEG FPGA SOC project ////
//// ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// - rewrite the register file and data path ////
//// Author(s): ////
//// - Alex Li, Alexli8055@hotmail.com ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Li datou ////
//// Alexli8055@hotmail.com ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// ARM, the ARM Powered logo, Thumb, and StrongARM are ////
//// registerd trademarks of ARM Limited, this core is simply ////
//// build for fun, please do not use for commerical propose ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Date of Creation: 2006.11.28 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description ////
//// leg FPGA SOC top module. ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "leg_define.v"
module leg_soc(
//memory interface, duplex by sdram and flash
sdram_clk,
flash_clk,
ncs,
nwe,
ncas,
nras,
dqm,
sdram_bank_sel,
mem_addr,
mem_data,
//uart if
//external interrupt if
//A/D if
//D/A if
//I2C bus if
//system clock and rst
clk,
rst
);
//sdram if, design for mt48lc4m32
output sdram_clk;
output flash_clk;
output [3:0] ncs;
output nwe;
output ncas;
output nras;
output [3:0] dqm;
output [3:0] sdram_bank_sel; //
output [23:0] mem_addr;
inout [31:0] mem_data;
//system
input clk;
input rst;
////////////////////////////////////////////////////////////
// 1) leg core connection //
////////////////////////////////////////////////////////////
// a) data path
wire d_re_from_core;
wire d_we_from_core;
wire [31:0] d_addr_from_core;
wire [31:0] d_data_to_core;
wire [31:0] d_data_from_core;
wire d_wait_to_core;
wire [3:0] d_be_from_core;
wire [31:0] d_data_from_dc;
// b) instruction path
wire [31:0] i_cache_data;
wire [31:0] i_addr_from_core;
wire i_read_from_core;
wire i_wait_to_core;
// c) dc related control signals
wire d_wait_from_dc;
wire d_re_to_dc;
wire d_we_to_dc;
reg [31:0] d_last_addr_r;
reg d_re_to_dc_d;
//memory space signals
wire [31:0] ic_adr_o;
wire [31:0] ic_dat_i;
wire ic_stb_o;
wire ic_cyc_o;
wire ic_ack_i;
wire [3:0] ic_sel_o;
wire [3:0] ic_tgd_i;
wire [3:0] ic_tgd_o;
wire ic_we_o;
wire [31:0] dc_adr_o;
wire [31:0] dc_dat_i;
wire [31:0] dc_dat_o;
wire dc_stb_o;
wire dc_cyc_o;
wire dc_ack_i;
wire [3:0] dc_sel_o;
wire [3:0] dc_tgd_i;
wire [3:0] dc_tgd_o;
wire dc_we_o;
//interrupt to the core
wire fiq_to_core;
wire irq_to_core;
wire [1:0] d_irq;
//none cachable memory signals
wire [31:0] d_data_from_mem;
wire d_wait_from_mem;
wire d_re_to_mem;
wire d_we_to_mem;
wire [3:0] d_be_to_mem;
//top level module of the leg core
leg leg_top(
//data path
.d_irq(2'b0),
.d_re(d_re_from_core),
.d_we(d_we_from_core),
.d_addr(d_addr_from_core),
.d_datain(d_data_to_core),
.d_dataout(d_data_from_core),
.d_wait(d_wait_to_core),
.d_be(d_be_from_core),
//instr path
.i_datain(i_cache_data),
.i_addr(i_addr_from_core),
.i_read(i_read_from_core),
.i_wait(i_wait_to_core),
//system
.clk(clk),
.rst(rst)
);
//top level module of the instruction cache
leg_icache ic_top(
//to cpu
.i_address(i_addr_from_core),
.i_dataout(i_cache_data),
.i_read(i_read_from_core),
.i_wait(i_wait_to_core),
//to coprocessor
.ic_control(1'b0),
//to mem bus
.ADR_O(ic_adr_o),
.DAT_I(ic_dat_i),
.STB_O(ic_stb_o),
.CYC_O(ic_cyc_o),
.ACK_I(ic_ack_i),
.SEL_O(ic_sel_o),
.TGD_I(ic_tgd_i),
.TGD_O(ic_tgd_o),
.WE_O(ic_we_o),
//system
.clk(clk),
.rst(rst)
);
//signal processing for the non cachable address and related signals
//address space 0x01c00000 to 0x01f00000 are not cachable
//the same space as the s344b0x
assign d_re_to_dc = (d_addr_from_core[31:22] != 10'b0000_0001_11 && d_re_from_core)? 1'b1 : 1'b0;
assign d_we_to_dc = (d_addr_from_core[31:22] != 10'b0000_0001_11 && d_we_from_core)? 1'b1 : 1'b0;
//
assign d_wait_to_core = d_wait_from_dc | d_wait_from_mem;
//from d cache or memory space
assign d_data_to_core = (d_re_to_dc_d)? d_data_from_dc : d_data_from_mem;
always@(posedge clk or posedge rst)
begin
if (rst) begin
d_last_addr_r <= 32'h0;
d_re_to_dc_d <= 1'b0;
end
else begin
if (d_re_from_core) begin //reserve the last address , for the wait signal arbitor
d_last_addr_r <= d_addr_from_core;
//use this signal for the data arbitor
if (d_re_to_dc)
d_re_to_dc_d <= 1'b1;
else
d_re_to_dc_d <= 1'b0;
end
end
end
//top level module of the data cache
leg_dcache dc_top(
//to cpu
.d_address(d_addr_from_core),
.d_wait(d_wait_from_dc),
.d_re(d_re_to_dc),
.d_we(d_we_to_dc),
.d_datain(d_data_from_core),
.d_dataout(d_data_from_dc),
.d_be(d_be_from_core),
//to coprocessor
.dc_control(1'b0),
//to mem bus
.ADR_O(dc_adr_o),
.DAT_I(dc_dat_i),
.DAT_O(dc_dat_o),
.STB_O(dc_stb_o),
.CYC_O(dc_cyc_o),
.ACK_I(dc_ack_i),
.SEL_O(dc_sel_o),
.TGD_I(dc_tgd_i),
.TGD_O(dc_tgd_o),
.WE_O(dc_we_o),
//system
.clk(clk),
.rst(rst)
);
//irq connection
//d_irq[0] = irq
//d_irq[1] = fiq
assign d_irq = {fiq_to_core,irq_to_core};
assign d_be_to_mem = d_be_from_core;
assign d_re_to_mem = (d_addr_from_core[31:22] == 10'b0000_0001_11 && d_re_from_core)? 1'b1 : 1'b0;
assign d_we_to_mem = (d_addr_from_core[31:22] == 10'b0000_0001_11 && d_we_from_core)? 1'b1 : 1'b0;
leg_mem_arbitor mem_controller_inst(
//i_cache if
.ic_adr_i(ic_adr_o),
.ic_dat_o(ic_dat_i),
.ic_stb_i(ic_stb_o),
.ic_cyc_i(ic_cyc_o),
.ic_ack_o(ic_ack_i),
.ic_sel_i(ic_sel_o),
.ic_tgd_o(ic_tgd_i),
.ic_tgd_i(ic_tgd_o),
//d_cache if
.dc_adr_i(dc_adr_o),
.dc_dat_o(dc_dat_i),
.dc_dat_i(dc_dat_o),
.dc_stb_i(dc_stb_o),
.dc_cyc_i(dc_cyc_o),
.dc_ack_o(dc_ack_i),
.dc_sel_i(dc_sel_o),
.dc_tgd_o(dc_tgd_i),
.dc_tgd_i(dc_tgd_o),
.dc_we_i (dc_we_o),
//none cacheable data to core
.d_address(d_addr_from_core),
.d_wait(d_wait_from_mem),
.d_re(d_re_to_mem),
.d_we(d_we_to_mem),
.d_datain(d_data_from_core),
.d_dataout(d_data_from_mem),
.d_be(d_be_to_mem),
//to sdram controller
//to flash controller
//to slow peripheral
//system clock
.clk(clk),
.rst(rst)
);
//sdram controller here
//flash controller here
//uart here
//timer here
//........
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -