📄 leg_shifter.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// LEG cpu core ////
//// ////
//// This file is part of the LEG FPGA SOC project ////
//// ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// - rewrite the register file and data path ////
//// Author(s): ////
//// - Alex Li, Alexli8055@hotmail.com ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2007 Li datou ////
//// Alexli8055@hotmail.com ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// ARM, the ARM Powered logo, Thumb, and StrongARM are ////
//// registerd trademarks of ARM Limited, this core is simply ////
//// build for fun, please do not use for commerical propose ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Date of Creation: 2006.11.28 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description ////
//// leg core barrier shifter module. ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "leg_define.v"
//`define SHIFT_BY_MULTIPLY
module leg_shifter(
din,
dout,
shift_oprand,
direction,
mode,
carry_in,
carry_out
);
//lsl logic shift left, low bits are set to zero-------- mode 0
//lsr logic shift right, high bits are set to zero ----- mode 1
//asr arithmetic shift right, with flag extendsiom ----- mode 2
//ror rotate right-------------------------------------- mode 3
//rrx rotate with carry--------------------------------- mode 4
input [31:0] din;
output [31:0] dout;
input [4:0] shift_oprand;
input direction;
input [2:0] mode;
input carry_in;
output carry_out;
`ifdef SHIFT_BY_MULTIPLY
wire [63:0] mul_result;
wire [31:0] dcontrol;
wire [31:0] shl
assign dcontrol = (mode == 3'b000)? 32'h00000001 << shift_oprand :
(mode == 3'b001)? 32'h80000000 >> shift_oprand : 32'h1;
assign mul_result = din * dcontrol;
assign dout = (direction)? mul_result[31:0] :
(mode[2])? {carry_in,din[31:1]} :
(mode == 3'b011) ? mul_result[31:0] | mul_result[63:32] :
mul_result[63:32];
`else
wire [31:0] lda;
wire [31:0] ldb;
wire [31:0] ldc;
wire [31:0] ldd;
wire [31:0] lde;
wire [31:0] rda;
wire [31:0] rdb;
wire [31:0] rdc;
wire [31:0] rdd;
wire [31:0] rde;
wire [15:0] lca;
wire [07:0] lcb;
wire [03:0] lcc;
wire [01:0] lcd;
wire lce;
wire [15:0] rca;
wire [07:0] rcb;
wire [03:0] rcc;
wire [01:0] rcd;
wire rce;
wire carry_selection_left;
wire carry_selection_right;
wire carry_out;
wire [31:0] dout;
assign lda = (shift_oprand[4])? {din[15:00], lca} : din;
assign ldb = (shift_oprand[3])? {lda[23:00], lcb} : lda;
assign ldc = (shift_oprand[2])? {ldb[27:00], lcc} : ldb;
assign ldd = (shift_oprand[1])? {ldc[29:00], lcd} : ldc;
assign lde = (shift_oprand[0])? {ldd[30:00], lce} : ldd;
assign rda = (shift_oprand[4])? {rca, din[31:16]} : din;
assign rdb = (shift_oprand[3])? {rcb, rda[31:08]} : rda;
assign rdc = (shift_oprand[2])? {rcc, rdb[31:04]} : rdb;
assign rdd = (shift_oprand[1])? {rcd, rdc[31:02]} : rdc;
assign rde = (shift_oprand[0] || mode[2])? {rce, rdd[31:01]} : rdd;
//shift left does not need any rotation
assign lca = 16'h0;
assign lcb = 8'h0;
assign lcc = 4'h0;
assign lcd = 2'h0;
assign lce = 1'h0;
assign rca = (mode[1:0] == 2'b11)? din[15:0] : (mode[1:0] == 2'b10)? {16{din[31]}} : 16'h0 ;
assign rcb = (mode[1:0] == 2'b11)? rda[07:0] : (mode[1:0] == 2'b10)? { 8{din[31]}} : 8'h0 ;
assign rcc = (mode[1:0] == 2'b11)? rdb[03:0] : (mode[1:0] == 2'b10)? { 4{din[31]}} : 4'h0 ;
assign rcd = (mode[1:0] == 2'b11)? rdc[01:0] : (mode[1:0] == 2'b10)? { 2{din[31]}} : 2'h0 ;
assign rce = (mode[2])? carry_in : (mode[1:0] == 2'b11)? rdd[0] : (mode[1:0] == 2'b10)? din[31] : 1'b0 ;
assign carry_selection_left = (shift_oprand[4:0] == 5'd01) ? din[31] :
(shift_oprand[4:0] == 5'd02) ? din[30] :
(shift_oprand[4:0] == 5'd03) ? din[29] :
(shift_oprand[4:0] == 5'd04) ? din[28] :
(shift_oprand[4:0] == 5'd05) ? din[27] :
(shift_oprand[4:0] == 5'd06) ? din[26] :
(shift_oprand[4:0] == 5'd07) ? din[25] :
(shift_oprand[4:0] == 5'd08) ? din[24] :
(shift_oprand[4:0] == 5'd09) ? din[23] :
(shift_oprand[4:0] == 5'd10) ? din[22] :
(shift_oprand[4:0] == 5'd11) ? din[21] :
(shift_oprand[4:0] == 5'd12) ? din[20] :
(shift_oprand[4:0] == 5'd13) ? din[19] :
(shift_oprand[4:0] == 5'd14) ? din[18] :
(shift_oprand[4:0] == 5'd15) ? din[17] :
(shift_oprand[4:0] == 5'd16) ? din[16] :
(shift_oprand[4:0] == 5'd17) ? din[15] :
(shift_oprand[4:0] == 5'd18) ? din[14] :
(shift_oprand[4:0] == 5'd19) ? din[13] :
(shift_oprand[4:0] == 5'd20) ? din[12] :
(shift_oprand[4:0] == 5'd21) ? din[11] :
(shift_oprand[4:0] == 5'd22) ? din[10] :
(shift_oprand[4:0] == 5'd23) ? din[09] :
(shift_oprand[4:0] == 5'd24) ? din[08] :
(shift_oprand[4:0] == 5'd25) ? din[07] :
(shift_oprand[4:0] == 5'd26) ? din[06] :
(shift_oprand[4:0] == 5'd27) ? din[05] :
(shift_oprand[4:0] == 5'd28) ? din[04] :
(shift_oprand[4:0] == 5'd29) ? din[03] :
(shift_oprand[4:0] == 5'd30) ? din[02] :
(shift_oprand[4:0] == 5'd31) ? din[01] : din[0];
assign carry_selection_right = (shift_oprand[4:0] == 5'd01) ? din[00] :
(shift_oprand[4:0] == 5'd02) ? din[01] :
(shift_oprand[4:0] == 5'd03) ? din[02] :
(shift_oprand[4:0] == 5'd04) ? din[03] :
(shift_oprand[4:0] == 5'd05) ? din[04] :
(shift_oprand[4:0] == 5'd06) ? din[05] :
(shift_oprand[4:0] == 5'd07) ? din[06] :
(shift_oprand[4:0] == 5'd08) ? din[07] :
(shift_oprand[4:0] == 5'd09) ? din[08] :
(shift_oprand[4:0] == 5'd10) ? din[09] :
(shift_oprand[4:0] == 5'd11) ? din[10] :
(shift_oprand[4:0] == 5'd12) ? din[11] :
(shift_oprand[4:0] == 5'd13) ? din[12] :
(shift_oprand[4:0] == 5'd14) ? din[13] :
(shift_oprand[4:0] == 5'd15) ? din[14] :
(shift_oprand[4:0] == 5'd16) ? din[15] :
(shift_oprand[4:0] == 5'd17) ? din[16] :
(shift_oprand[4:0] == 5'd18) ? din[17] :
(shift_oprand[4:0] == 5'd19) ? din[18] :
(shift_oprand[4:0] == 5'd20) ? din[19] :
(shift_oprand[4:0] == 5'd21) ? din[20] :
(shift_oprand[4:0] == 5'd22) ? din[21] :
(shift_oprand[4:0] == 5'd23) ? din[22] :
(shift_oprand[4:0] == 5'd24) ? din[23] :
(shift_oprand[4:0] == 5'd25) ? din[24] :
(shift_oprand[4:0] == 5'd26) ? din[25] :
(shift_oprand[4:0] == 5'd27) ? din[26] :
(shift_oprand[4:0] == 5'd28) ? din[27] :
(shift_oprand[4:0] == 5'd29) ? din[28] :
(shift_oprand[4:0] == 5'd30) ? din[29] :
(shift_oprand[4:0] == 5'd31) ? din[30] : din[0];
assign dout= (direction) ? lde : rde;
assign carry_out = (direction) ? carry_selection_left : carry_selection_right;
`endif //end of none multiplier inplementation
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