_primary.vhd

verilog hdl编写,六段流水线CPU.程序完整

library verilog;
use verilog.vl_types.all;
entity leg_rf is
    port(
        raddra          : in     vl_logic_vector(4 downto 0);
        raddrb          : in     vl_logic_vector(4 downto 0);
        raddrc          : in     vl_logic_vector(4 downto 0);
        rdataa          : out    vl_logic_vector(31 downto 0);
        rdatab          : out    vl_logic_vector(31 downto 0);
        rdatac          : out    vl_logic_vector(31 downto 0);
        waddra          : in     vl_logic_vector(4 downto 0);
        waddrb          : in     vl_logic_vector(4 downto 0);
        wdataa          : in     vl_logic_vector(31 downto 0);
        wdatab          : in     vl_logic_vector(31 downto 0);
        a_foward_ena    : in     vl_logic;
        w_foward_ena    : in     vl_logic;
        wea             : in     vl_logic;
        web             : in     vl_logic;
        d_en            : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end leg_rf;