📄 lac_adder16.fit.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 27 00:00:32 2005 " "Info: Processing started: Sun Nov 27 00:00:32 2005" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off LAC_adder16 -c LAC_adder16 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LAC_adder16 -c LAC_adder16" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "LAC_adder16 EP1C3T144C6 " "Info: Selected device EP1C3T144C6 for design \"LAC_adder16\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C6 " "Info: Device EP1C6T144C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "51 51 " "Info: No exact pin location assignment(s) for 51 pins of 51 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[0\] " "Info: Pin s\[0\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[0\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[0] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[1\] " "Info: Pin s\[1\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[1\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[1] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[2\] " "Info: Pin s\[2\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[2\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[2] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[3\] " "Info: Pin s\[3\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[3\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[3] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[4\] " "Info: Pin s\[4\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[4\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[4] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[5\] " "Info: Pin s\[5\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[5\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[5] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[6\] " "Info: Pin s\[6\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[6\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[6] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[7\] " "Info: Pin s\[7\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[7\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[7] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[8\] " "Info: Pin s\[8\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[8\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[8] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[9\] " "Info: Pin s\[9\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[9\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[9] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[10\] " "Info: Pin s\[10\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[10\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[10] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[11\] " "Info: Pin s\[11\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[11\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[11] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[12\] " "Info: Pin s\[12\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[12\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[12] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[13\] " "Info: Pin s\[13\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[13\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[13] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[14\] " "Info: Pin s\[14\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[14\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[14] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "s\[15\] " "Info: Pin s\[15\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 4 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "s\[15\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { s[15] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { s[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "p_out " "Info: Pin p_out not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 5 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "p_out" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { p_out } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { p_out } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "g_out " "Info: Pin g_out not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 5 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "g_out" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { g_out } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { g_out } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "cin " "Info: Pin cin not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 3 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "cin" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { cin } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { cin } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[0\] " "Info: Pin a\[0\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[0\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[0] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[0\] " "Info: Pin b\[0\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[0\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[0] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[1\] " "Info: Pin a\[1\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[1\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[1] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[1\] " "Info: Pin b\[1\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[1\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[1] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[2\] " "Info: Pin a\[2\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[2\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[2] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[2\] " "Info: Pin b\[2\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[2\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[2] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[3\] " "Info: Pin a\[3\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[3\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[3] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[3\] " "Info: Pin b\[3\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[3\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[3] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[4\] " "Info: Pin a\[4\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[4\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[4] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[4\] " "Info: Pin b\[4\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[4\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[4] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[5\] " "Info: Pin a\[5\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[5\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[5] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[5\] " "Info: Pin b\[5\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[5\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[5] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[6\] " "Info: Pin a\[6\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[6\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[6] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[6\] " "Info: Pin b\[6\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[6\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[6] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[7\] " "Info: Pin a\[7\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[7\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[7] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[7\] " "Info: Pin b\[7\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[7\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[7] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[8\] " "Info: Pin a\[8\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[8\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[8] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[8\] " "Info: Pin b\[8\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[8\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[8] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[9\] " "Info: Pin a\[9\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[9\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[9] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[9\] " "Info: Pin b\[9\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[9\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[9] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[10\] " "Info: Pin a\[10\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[10\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[10] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[10\] " "Info: Pin b\[10\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[10\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[10] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[11\] " "Info: Pin a\[11\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[11\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[11] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[11\] " "Info: Pin b\[11\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[11\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[11] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[12\] " "Info: Pin a\[12\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[12\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[12] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[12\] " "Info: Pin b\[12\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[12\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[12] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[13\] " "Info: Pin a\[13\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[13\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[13] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[13\] " "Info: Pin b\[13\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[13\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[13] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[14\] " "Info: Pin a\[14\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[14\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[14] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[14\] " "Info: Pin b\[14\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[14\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[14] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a\[15\] " "Info: Pin a\[15\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "a\[15\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { a[15] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { a[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b\[15\] " "Info: Pin b\[15\] not assigned to an exact location on the device" { } { { "LAC_adder16.v" "" { Text "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.v" 2 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "b\[15\]" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "LAC_adder16" "UNKNOWN" "V1" "D:/documents/FPGA/study/LAC_adder16/db/LAC_adder16.quartus_db" { Floorplan "D:/documents/FPGA/study/LAC_adder16/" "" "" { b[15] } "NODE_NAME" } "" } } { "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" { Floorplan "D:/documents/FPGA/study/LAC_adder16/LAC_adder16.fld" "" "" { b[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" { } { } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" { } { } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
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