lac_adder16.fit.rpt

十六位超前进位加法器

Fitter report for LAC_adder16
Sun Nov 27 00:00:36 2005
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Pad To Core Delay Chain Fanout
 16. Non-Global High Fan-Out Signals
 17. Interconnect Usage Summary
 18. LAB Logic Elements
 19. LAB Signals Sourced
 20. LAB Signals Sourced Out
 21. LAB Distinct Inputs
 22. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Sun Nov 27 00:00:36 2005    ;
; Quartus II Version    ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name         ; LAC_adder16                              ;
; Top-level Entity Name ; LAC_adder16                              ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C3T144C6                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 76 / 2,910 ( 3 % )                       ;
; Total pins            ; 51 / 104 ( 49 % )                        ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0 / 59,904 ( 0 % )                       ;
; Total PLLs            ; 0 / 1 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                        ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                               ; Setting                        ; Default Value                  ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                               ; EP1C3T144C6                    ;                                ;
; SignalProbe signals routed during normal compilation ; Off                            ; Off                            ;
; Use smart compilation                                ; Off                            ; Off                            ;
; Router Timing Optimization Level                     ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                             ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                 ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                          ; Off                            ; Off                            ;
; Optimize Timing                                      ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing           ; On                             ; On                             ;
; Limit to One Fitting Attempt                         ; Off                            ; Off                            ;
; Final Placement Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations          ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                        ; 1                              ; 1                              ;
; Slow Slew Rate                                       ; Off                            ; Off                            ;
; PCI I/O                                              ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic   ; Off                            ; Off                            ;
; Perform Register Duplication                         ; Off                            ; Off                            ;
; Perform Register Retiming                            ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                            ; Off                            ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto                           ; Auto                           ;