diriver.v

来自「基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制 」· Verilog 代码 · 共 62 行

/* 步进电机驱动  */

module DIRIVER (CLK, CLR, DIR, OUT);
    input   CLR, DIR, CLK;
    output  [3:0] OUT;
    wire    [1:0] Q;

    COUNT_UP_DOWN  COUNT_UP_DOWN (CLR, CLK, DIR, Q);
    DEC2_4  DEC2_4 (Q, OUT);

endmodule


/* COUNT_UP_DOWN */

module COUNT_UP_DOWN (CLR, CLK, DIR, Q);
    input   CLR, CLK, DIR;
    output  [1:0] Q;
    reg     [1:0] Q;

    
    always  @(posedge CLK or negedge CLR) 
      begin
       if (!CLR)
            Q=0;
       else 
         begin
          if (!DIR)
               Q=Q+1;
          else 
               Q=Q-1;
         end
      end	
    
endmodule


/* DEC2_4 */

`define  OUT_0  4'b0001 
`define  OUT_1  4'b0010 
`define  OUT_2  4'b0100
`define  OUT_3  4'b1000

module  DEC2_4 (IN, OUT);
      input  [1:0] IN;
      output [3:0] OUT;

      assign OUT=FUNC_DEC(IN);

      function [3:0] FUNC_DEC;
         input [1:0] IN;

         case (IN)
           2'b00: FUNC_DEC=`OUT_0;
           2'b01: FUNC_DEC=`OUT_1;
           2'b10: FUNC_DEC=`OUT_2;
           2'b11: FUNC_DEC=`OUT_3;
         endcase
      endfunction
endmodule