count_up_down_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制 」· Verilog 代码 · 共 30 行

/* 加减法计数器的顶层模块  */


`timescale 1ps/1ps

module    COUNT_UP_DOWN_TEST;
     reg      CLR, CLK, DIR;
     wire     [1:0] Q;
     parameter  STEP=50;

     COUNT_UP_DOWN  COUNT_UP_DOWN (CLR, CLK, DIR, Q);

     always #(STEP/5)  CLK=~CLK;

     initial
        begin
          CLK=0; DIR=0; CLR=1;
          #(STEP/2)     CLR=0;
          #(STEP/2)     CLR=1;  
          #(STEP*3.5)   DIR=1;
          #(STEP)    
          #(STEP*3)     DIR=0;
          #(STEP)      
          #(STEP)   $finish;
        end
endmodule