pulse_level_g_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.6 脉冲高电平和低电平持续时」· Verilog 代码 · 共 42 行

`timescale 1us / 1us
						
module PULSE_LEVEL_G_TEST;		
    reg    CLK, CLKX, RST;               
    wire   [16:0] H_LEVEL;
    wire   [7:0]  L_LEVEL;   
          
						
    PULSE_LEVEL_G PULSE_LEVEL_G (CLK, CLKX, RST, H_LEVEL, L_LEVEL); 

    always  #500   CLK=~CLK;

    initial
      begin:CLOCK
        parameter ON=5000, OFF=1000; 
        CLKX=0;
        forever
          begin
            #OFF  CLKX=1'b1;
            #ON   CLKX=1'b0;
          end
      end

    initial
      begin
        CLK=0; RST=1;
        #100 RST=0; 
        #100 RST=1; 
        #40000 $finish;
        disable CLOCK;
      end

endmodule