pulse_level_s_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.6 脉冲高电平和低电平持续时」· Verilog 代码 · 共 40 行

`timescale 1us / 1us
						
module PULSE_LEVEL_S_TEST;		
    reg    PULSE;
    reg    CLK, RST;
    wire   PH;                   
    wire   [3:0] DP;              
    wire   [4:0] LD;              
    wire   [3:0] P;     
    wire   [7:0] LED;
          
	
    PULSE_LEVEL_S PULSE_LEVEL_S  (PULSE, CLK, RST, PH, P, DP, LD, LED);

    always  #500   CLK=~CLK;

    initial
      begin:CLOCK
        parameter ON=6000, OFF=2000; 
        PULSE=0;
        forever
          begin
            #OFF  PULSE=1'b1;
            #ON   PULSE=1'b0;
          end
      end

    initial
      begin
        CLK=0; RST=1;
        #100 RST=0; 
        #100 RST=1; 
        #30000 $finish;
        disable CLOCK;
      end

endmodule