pulse_width.v

来自「基于Verilog-HDL的硬件电路的实现 9.5 脉冲周期的测量与显示 」· Verilog 代码 · 共 49 行

module  PULSE_WIDTH  (CLK, CLKX, RST, WIDTH);   
    input    CLK, CLKX, RST;
    output   [16:0] WIDTH; 
    reg      [16:0] WIDTH;  
    reg      [16:0] OUT; 
    reg      CNT_EN;
    reg      LOAD;
    wire     CNT_CLR;                


    always @ (posedge CLKX or negedge RST)
       begin
         if (!RST)
           begin
             CNT_EN=0;
             LOAD=1;
           end
         else 
           begin
             CNT_EN=~CNT_EN;
             LOAD=~CNT_EN;
           end
        end
				
    assign CNT_CLR=~(~CLKX & LOAD);

    always @(posedge CLK or negedge CNT_CLR)
       begin
        if (!CNT_CLR)   
           OUT=0;
        else if (CNT_EN)
           begin
             if (OUT==999999)
                 OUT=999999;
             else 
                 OUT=OUT+1;
           end
       end

    always @ (posedge LOAD)
       begin
         WIDTH=OUT;
       end
endmodule