pulse_width_g.v

来自「基于Verilog-HDL的硬件电路的实现 9.5 脉冲周期的测量与显示 」· Verilog 代码 · 共 67 行

/** 计算脉冲宽度 **/

module  PULSE_WIDTH_G  (CLK, CLKX, RST, WIDTH);   
    input    CLK, CLKX, RST;
    output   [16:0] WIDTH; 
    reg      [16:0] WIDTH; 
    reg      [16:0] OUT;   
    reg      CNT_EN;
    reg      LOAD;
    wire     CNT_CLR; 
    wire     CLK_M, CLKX_M;    
    reg      [3:0] Q;           

    assign   CLKX_M=CLKX & (Q[3]|Q[2]|Q[1]|Q[0]); 

    always @ (posedge CLKX_M or negedge RST)
       begin
         if (!RST)
           begin
             Q=9;
             CNT_EN=0;
             LOAD=1;
           end
         else if (Q==0)
           begin
             Q=0;
             CNT_EN=0;
           end
         else
           begin
             Q=Q-1;
             CNT_EN=~CNT_EN;
             LOAD=~CNT_EN;	
           end
        end
    
			
    assign   CNT_CLR=~(~CLKX_M&~CNT_EN);

    assign   CLK_M=CLK & (Q[3]|Q[2]|Q[1]|Q[0]);

    always @(posedge CLK_M or negedge CNT_CLR)
       begin
        if (!CNT_CLR)   
           OUT=0;
        else if (CNT_EN)
           begin
             if (OUT==99999)
               begin
                 OUT=99999;
               end
             else
               begin
                 OUT=OUT+1;
               end
           end
       end

    always @ (posedge LOAD)
       begin
         WIDTH=OUT;
       end
endmodule