pulse_width_s_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.5 脉冲周期的测量与显示 」· Verilog 代码 · 共 37 行

`timescale 1us / 1us
						
module PULSE_WIDTH_S_TEST;		
    reg    PULSE;
    reg    CLK, RST;
    wire   PH;                   
    wire   [3:0] DP;              
    wire   [4:0] LD;              
    wire   [3:0] P;     
          
	
    PULSE_WIDTH_S PULSE_WIDTH_S (PULSE, CLK, RST, PH, P, DP, LD);

    always  #500   CLK=~CLK;

   initial
      begin:CLOCK
        PULSE=0; 
        forever  
          begin  
           #3000 PULSE=~PULSE;
          end
      end

    initial
      begin:SIMULATION
        CLK=0; RST=1; 
        #10  RST=0;
        #10  RST=1;                     
        #30000  $finish;
        disable CLOCK;
      end

endmodule