pulse_fre.v

来自「基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示 」· Verilog 代码 · 共 51 行

module PULSE_FRE (CLK, CLKX, RST, FRE);
    input   CLK, RST, CLKX;
    output  [16:0] FRE;
    reg     [16:0] FRE;
    reg     [16:0] OUT;
    reg     CNT_EN, LOAD;
    wire    CNT_CLR;

    always @ (posedge CLK or negedge RST)
       begin
         if (!RST)
           begin
             CNT_EN=0;
             LOAD=1;
           end
         else 
           begin
             CNT_EN=~CNT_EN;
             LOAD=~CNT_EN;
           end
        end

    assign CNT_CLR=~(~CLK&LOAD);

    always @(posedge CLKX or negedge CNT_CLR)
       begin
        if (!CNT_CLR)   
           OUT=0;
        else if (CNT_EN)
           begin
             if (OUT==99999)
                 OUT=99999;
	     else
                 OUT=OUT+1;
           end
       end

    always @(posedge LOAD)
       begin
          FRE=OUT;
       end

endmodule