pulse_fre_s_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示 」· Verilog 代码 · 共 33 行

`timescale 1ms / 1ms
						
module PULSE_FRE_S_TEST;
    reg      PULSE, CLK, RST;
    wire     PH;                   
    wire     [3:0] DP;              
    wire     [4:0] LD;              
    wire     [3:0] P; 	
    integer  I;	
						
    PULSE_FRE_S  PULSE_FRE_S  (PULSE, CLK, RST, PH, P, DP, LD);

    always #500 CLK=~CLK;
	
    initial
      begin
        CLK=0; PULSE=0; RST=1; 
        #10  RST=0;
        #10  RST=1;   I=0;    
          

        while (I<150)  
          begin  
           #100 I=I+1;
           PULSE=~PULSE;
          end

        $finish;
      end

endmodule