pulse_fre_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示 」· Verilog 代码 · 共 30 行

`timescale 1ms / 1ms
						
module PULSE_FRE_TEST;		
    reg     CLK, CLKX, RST;               
    wire    [16:0] FRE;   
    integer I;  
						
    PULSE_FRE PULSE_FRE (CLK, CLKX, RST, FRE);

    always #500 CLK=~CLK;

    initial
      begin
        CLK=0; CLKX=0; RST=1; 
        #10  RST=0;
        #10  RST=1; I=0;   
          

        while (I<100)  
          begin  
           #50  I=I+1;
             CLKX=~CLKX;
          end 

        $finish;
      end
endmodule