p_detect.v

来自「基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 」· Verilog 代码 · 共 54 行

//********************************************
// 输入检测模块
//******************************************* 


`timescale	1ns/1ns
module ONE_PULSE ( CLK, OUT, RB, KEY);
   input  CLK, RB, KEY;
   output OUT;
       
   P_DETECT   M_DETECT( RB, CLK, ~KEY, OUT);

endmodule

//******************** P_DETECT
module P_DETECT( RB, CLK, IN, P_Q);
   input  IN, CLK, RB;
   output P_Q;

   DFF_R  U1 ( CLK2 , IN & P_QB, P_Q, P_QB, RB);
   TFF     U2 ( P_Q, T_QB, RB);
   assign  CLK2 = CLK & T_QB;

endmodule

//******************** DFF_R
module DFF_R( CK, D, Q, QB, RB);
   input  CK, D, RB;
   output Q, QB;
   reg    Q;

   always @( negedge CK or negedge RB ) begin
      if ( RB==0 )
          Q <= 0;
      else
          Q <= D;
   end
   assign QB = ~Q;
endmodule

//******************** TFF
module TFF( T, QB, RB );
   input  T, RB;
   output QB;
   reg    QB;

   always @( posedge T or negedge RB ) begin
       if ( RB==0 )
          QB <= 1;
       else  
          QB <= ~QB;
   end
endmodule