p_detect_test.v

基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 9.1.1 由系统功能描述时序关系 9.1.2 流程图的设计 9.1.3 系统功能描述

//********************************************
// 输入检测模块测试程序  
//*******************************************

`timescale    1ns/1ns
module    ONE_PULSE_TEST; 
   reg    CLK, RB;
   reg    KEY;
   wire   OUT;
   parameter   STEP=50;

   ONE_PULSE   ONE_PULSE(CLK, OUT, RB, KEY);

   always   #(STEP/5)     CLK=~CLK;

   initial    begin
       RB=1; CLK=0; KEY=1;
       #(STEP)       RB=0;
       #(STEP/5)     RB=1; 
       #(STEP)       KEY=0;
       #(STEP)       KEY=1;
       #(STEP)
       #(STEP)       KEY=0;
       #(STEP)       KEY=1;
       #(STEP)
       #(STEP)       RB=0;
       #(STEP/5)     RB=1;
       #(STEP)
       #(STEP)
       #(STEP)      
       #(STEP)       KEY=0;
       #(STEP)       KEY=1;
       #(STEP)    
       #(STEP)
       #(STEP)
       #(STEP) 
       #(STEP/2)    $finish;
   end
endmodule