one_pulse_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 」· Verilog 代码 · 共 45 行

//********************************************
// 可编程单脉冲发生器 测试程序
//*******************************************

`timescale    1us/1us
module    ONE_PULSE_TEST; 
   reg    CLK, RB, KEY;
   reg   [7:0] DATA_IN;
   wire  P_PULSE;
   parameter   STEP=50;

   ONE_PULSE  ONE_PULSE ( CLK, RB, DATA_IN, P_PULSE, KEY);

   always   #(STEP/3)     CLK=~CLK;

   initial
        begin
            RB=1;CLK=0;KEY=1;
  	    #(STEP)     DATA_IN = 8'b0000_1010;
            #(STEP)     RB=0;
            #(STEP/2)   RB=1; 
	    #(STEP)
	    #(STEP)
	    #(STEP/2)
            #(STEP)     KEY=0;
	    #(STEP/2)
            #(STEP)     KEY=1;
	    #(STEP)
            #(STEP)
            #(STEP)     KEY=0;
            #(STEP)     KEY=1;
	    #(STEP)
            #(STEP)
            #(STEP)
            #(STEP)     KEY=0;
            #(STEP)     KEY=1;
	    #(STEP)
            #(STEP)
            #(STEP) 
            #(STEP/2)    $finish;
      end
endmodule