p_dly_2_test.v

来自「基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 」· Verilog 代码 · 共 34 行

//********************************************
// 延时模块测试程序
//*******************************************   


`timescale    1ns/1ns
module    ONE_PULSE_TEST; 
   reg    CLK, RB;
   wire  DLY_OUT;
   parameter   STEP=50;

   ONE_PULSE ONE_PULSE ( CLK, RB, DLY_OUT);

   always   #(STEP/5)     CLK=~CLK;

   initial   begin
            RB=1; CLK=0;
            #(STEP)       RB=0;
            #(STEP)     RB=1; 
            #(STEP)
            #(STEP)
            #(STEP)
            #(STEP)
            #(STEP)
            #(STEP)       RB=0;
            #(STEP/5)     RB=1;
	    #(STEP)
            #(STEP)
            #(STEP)
            #(STEP) 
            #(STEP/2)    $finish;
   end
endmodule