p_dly_2.v

基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 9.1.1 由系统功能描述时序关系 9.1.2 流程图的设计 9.1.3 系统功能描述

//********************************************
// 延时模块 
//*******************************************


`timescale	1ns/1ns
module  ONE_PULSE ( CLK, RB, DLY_OUT);
   input  CLK, RB;
   output DLY_OUT;
   
   P_DLY  U1 ( CLK, RB, DLY_OUT);   
endmodule

//******************** P_DLY
module P_DLY ( CLK, RB, DLY_OUT);
   input  CLK, RB;
   wire  Q, QB, CNT_CLK;
   output DLY_OUT;
   
   DFF_R  U1 ( CLK, Q, RB);
   assign  CNT_CLK = CLK & Q & QB;
   DELAY  U2 ( RB, CNT_CLK , DLY_OUT);
   TFF    U3 ( DLY_OUT, QB, RB );
endmodule

//********************  DELAY
module	DELAY	( RESET_B, CLK, DIV_CLK );
   input	RESET_B, CLK;
   output  DIV_CLK;
   reg	[2:0] Q;

   always  @( posedge CLK or negedge RESET_B )
      if ( !RESET_B )
	 Q <= 0;
      else if ( Q == 5 )
	 Q <= 0;
      else
	 Q <= Q + 1;
   
   assign DIV_CLK = ~(Q[2] & ~Q[1] & Q[0]);
endmodule

//******************** DFF_R
module DFF_R( CK, Q, RB);
   input  CK, RB;
   output Q;
   reg    Q;

   always @( negedge CK or negedge RB ) begin
         if ( RB==0 )
            Q <= 0;
         else
            Q <= 1;
   end
endmodule

//******************** TFF
module TFF( T, QB, RB );
   input  T, RB;
   output QB;
   reg    QB;

   always @( posedge T or negedge RB ) begin
        if ( RB==0 )
            QB <= 1;
        else  
            QB <= ~QB;
   end
endmodule