blocking.v

来自「基于verilog语言的数据选择器」· Verilog 代码 · 共 25 行

//------------blocking--------------------------
module blocking (clk,a,b,c,d,e);
    output[3:0]b,c,d,e;
    input[3:0]a;
    input clk;
    reg[3:0]b,c,d,e; 
  
    always @(posedge clk)
        begin 
              
         b=a;
         c=b;
         $display("Blocking:a=%d,b=%d,c=%d.",a,b,c);
       
         end
    always@(posedge clk) d=a;
 
      
    always@(posedge clk) e=d;
          
endmodule