transcript

来自「基于verilog语言的数据选择器」· 代码 · 共 26 行

# Reading G:/Program Files/Modeltech_6.0/win32/../tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "D:/exercise/blocking/block.mpf" 
# Loading project block
vsim work.compareTop
# vsim work.compareTop 
# Loading work.compareTop
# Loading work.blocking
# ** Warning: (vsim-3015) D:/exercise/blocking/compareTop.v(29): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'b'.
#         Region: /compareTop/n
# ** Warning: (vsim-3015) D:/exercise/blocking/compareTop.v(29): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'c'.
#         Region: /compareTop/n
# ** Warning: (vsim-3015) D:/exercise/blocking/compareTop.v(29): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'd'.
#         Region: /compareTop/n
# ** Warning: (vsim-3015) D:/exercise/blocking/compareTop.v(29): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'e'.
#         Region: /compareTop/n