lin.tan.qmsg

verilog HDL 编写的PWM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 24 00:05:53 2006 " "Info: Processing started: Fri Feb 24 00:05:53 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=on --export_settings_files=off lin -c lin " "Info: Command: quartus_tan --import_settings_files=on --export_settings_files=off lin -c lin" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node clock is an undefined clock" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 2 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register count\[1\] register count1\[11\] 55.56 MHz 18.0 ns Internal " "Info: Clock clock has Internal fmax of 55.56 MHz between source register count\[1\] and destination register count1\[11\] (period= 18.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.000 ns + Longest register register " "Info: + Longest register to register delay is 14.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC5 55 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 55; REG Node = 'count\[1\]'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "" { count[1] } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns lpm_add_sub:add_rtl_2\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[7\]~102 2 COMB LC21 10 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC21; Fanout = 10; COMB Node = 'lpm_add_sub:add_rtl_2\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[7\]~102'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "8.000 ns" { count[1] lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~102 } "NODE_NAME" } } } { "d:/altera/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/altera/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.000 ns count1\[11\] 3 REG LC15 23 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = LC15; Fanout = 23; REG Node = 'count1\[11\]'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "6.000 ns" { lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~102 count1[11] } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns 85.71 % " "Info: Total cell delay = 12.000 ns ( 85.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 14.29 % " "Info: Total interconnect delay = 2.000 ns ( 14.29 % )" {  } {  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "14.000 ns" { count[1] lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~102 count1[11] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock clock to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_87 34 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 34; CLK Node = 'clock'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns count1\[11\] 2 REG LC15 23 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC15; Fanout = 23; REG Node = 'count1\[11\]'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "0.000 ns" { clock count1[11] } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock count1[11] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.500 ns - Longest register " "Info: - Longest clock path from clock clock to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_87 34 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 34; CLK Node = 'clock'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns count\[1\] 2 REG LC5 55 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC5; Fanout = 55; REG Node = 'count\[1\]'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "0.000 ns" { clock count[1] } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock count[1] } "NODE_NAME" } } }  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock count1[11] } "NODE_NAME" } } } { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock count[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "14.000 ns" { count[1] lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~102 count1[11] } "NODE_NAME" } } } { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock count1[11] } "NODE_NAME" } } } { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock count[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock pwm pwm~reg0 5.000 ns register " "Info: tco from clock clock to destination pin pwm through register pwm~reg0 is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.500 ns + Longest register " "Info: + Longest clock path from clock clock to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clock 1 CLK PIN_87 34 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 34; CLK Node = 'clock'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns pwm~reg0 2 REG LC83 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC83; Fanout = 1; REG Node = 'pwm~reg0'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "0.000 ns" { clock pwm~reg0 } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock pwm~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm~reg0 1 REG LC83 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC83; Fanout = 1; REG Node = 'pwm~reg0'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "" { pwm~reg0 } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns pwm 2 PIN PIN_53 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'pwm'" {  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { pwm~reg0 pwm } "NODE_NAME" } } } { "F:/PWM/lin.v" "" "" { Text "F:/PWM/lin.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { pwm~reg0 pwm } "NODE_NAME" } } }  } 0}  } { { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { clock pwm~reg0 } "NODE_NAME" } } } { "F:/PWM/db/lin_cmp.qrpt" "" "" { Report "F:/PWM/db/lin_cmp.qrpt" Compiler "lin" "UNKNOWN" "V1" "F:/PWM/db/lin.quartus_db" { Floorplan "" "" "1.500 ns" { pwm~reg0 pwm } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 24 00:05:54 2006 " "Info: Processing ended: Fri Feb 24 00:05:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}