lin.map.eqn

verilog HDL 编写的PWM

F81L2 = F81L2_p1_out $ F81L2_or_out;


--count1[17] is count1[17]
count1[17]_p1_out = count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[17]_or_out = count1[17];
count1[17]_reg_input = count1[17]_p1_out $ count1[17]_or_out;
count1[17] = DFFE(count1[17]_reg_input, !GLOBAL(clock), , , );


--F81L3 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[2]~91
F81L3_p1_out = count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L3_or_out = count1[18];
F81L3 = F81L3_p1_out $ F81L3_or_out;


--count1[18] is count1[18]
count1[18]_p1_out = count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[18]_or_out = count1[18];
count1[18]_reg_input = count1[18]_p1_out $ count1[18]_or_out;
count1[18] = DFFE(count1[18]_reg_input, !GLOBAL(clock), , , );


--F81L4 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[3]~99
F81L4_p1_out = count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L4_or_out = count1[19];
F81L4 = F81L4_p1_out $ F81L4_or_out;


--count1[19] is count1[19]
count1[19]_p1_out = count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[19]_or_out = count1[19];
count1[19]_reg_input = count1[19]_p1_out $ count1[19]_or_out;
count1[19] = DFFE(count1[19]_reg_input, !GLOBAL(clock), , , );


--F81L5 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[4]~107
F81L5_p1_out = count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L5_or_out = count1[20];
F81L5 = F81L5_p1_out $ F81L5_or_out;


--count1[20] is count1[20]
count1[20]_p1_out = count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[20]_or_out = count1[20];
count1[20]_reg_input = count1[20]_p1_out $ count1[20]_or_out;
count1[20] = DFFE(count1[20]_reg_input, !GLOBAL(clock), , , );


--F81L6 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[5]~115
F81L6_p1_out = count1[20] & count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L6_or_out = count1[21];
F81L6 = F81L6_p1_out $ F81L6_or_out;


--count1[21] is count1[21]
count1[21]_p1_out = count1[20] & count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[21]_or_out = count1[21];
count1[21]_reg_input = count1[21]_p1_out $ count1[21]_or_out;
count1[21] = DFFE(count1[21]_reg_input, !GLOBAL(clock), , , );


--F81L7 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[6]~123
F81L7_p1_out = count1[21] & count1[20] & count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L7_or_out = count1[22];
F81L7 = F81L7_p1_out $ F81L7_or_out;


--count1[22] is count1[22]
count1[22]_p1_out = count1[21] & count1[20] & count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[22]_or_out = count1[22];
count1[22]_reg_input = count1[22]_p1_out $ count1[22]_or_out;
count1[22] = DFFE(count1[22]_reg_input, !GLOBAL(clock), , , );


--F81L8 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[7]~131
F81L8_p1_out = count1[22] & count1[21] & count1[20] & count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L8_or_out = count1[23];
F81L8 = F81L8_p1_out $ F81L8_or_out;


--count1[0] is count1[0]
count1[0]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L3 & F21L2 & F51L8 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[0]_or_out = count1[0]_p1_out # F21L1;
count1[0]_reg_input = !(count1[0]_or_out);
count1[0] = DFFE(count1[0]_reg_input, !GLOBAL(clock), , , );


--F21L2 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[1]~70
F21L2_p1_out = count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L2_or_out = count1[1];
F21L2 = F21L2_p1_out $ F21L2_or_out;


--count1[1] is count1[1]
count1[1]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L3 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[1]_or_out = count1[1]_p1_out # !F21L2;
count1[1]_reg_input = !(count1[1]_or_out);
count1[1] = DFFE(count1[1]_reg_input, !GLOBAL(clock), , , );


--F21L3 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~74
F21L3_p1_out = count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L3_or_out = count1[2];
F21L3 = F21L3_p1_out $ F21L3_or_out;


--count1[2] is count1[2]
count1[2]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L2 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[2]_or_out = count1[2]_p1_out # !F21L3;
count1[2]_reg_input = !(count1[2]_or_out);
count1[2] = DFFE(count1[2]_reg_input, !GLOBAL(clock), , , );


--F21L4 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~78
F21L4_p1_out = count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L4_or_out = count1[3];
F21L4 = F21L4_p1_out $ F21L4_or_out;


--count1[3] is count1[3]
count1[3]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L3 & F21L2 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[3]_or_out = count1[3]_p1_out # !F21L4;
count1[3]_reg_input = !(count1[3]_or_out);
count1[3] = DFFE(count1[3]_reg_input, !GLOBAL(clock), , , );


--F21L5 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~82
F21L5_p1_out = count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L5_or_out = count1[4];
F21L5 = F21L5_p1_out $ F21L5_or_out;


--count1[4] is count1[4]
count1[4]_p1_out = count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count1[4]_or_out = count1[4];
count1[4]_reg_input = count1[4]_p1_out $ count1[4]_or_out;
count1[4] = DFFE(count1[4]_reg_input, !GLOBAL(clock), , , );


--F21L6 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~90
F21L6_p1_out = count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L6_or_out = count1[5];
F21L6 = F21L6_p1_out $ F21L6_or_out;


--count1[5] is count1[5]
count1[5]_p1_out = !F21L8 & !F21L7 & !F21L5 & F21L4 & F21L3 & F21L2 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[5]_or_out = count1[5]_p1_out # !F21L6;
count1[5]_reg_input = !(count1[5]_or_out);
count1[5] = DFFE(count1[5]_reg_input, !GLOBAL(clock), , , );


--F21L7 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~94
F21L7_p1_out = count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L7_or_out = count1[6];
F21L7 = F21L7_p1_out $ F21L7_or_out;


--count1[6] is count1[6]
count1[6]_p1_out = count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count1[6]_or_out = count1[6];
count1[6]_reg_input = count1[6]_p1_out $ count1[6]_or_out;
count1[6] = DFFE(count1[6]_reg_input, !GLOBAL(clock), , , );


--F21L8 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~102
F21L8_p1_out = count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L8_or_out = count1[7];
F21L8 = F21L8_p1_out $ F21L8_or_out;


--base[7] is base[7]
base[7]_reg_input = VCC;
base[7]_p3_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L3 & F21L2 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
base[7] = TFFE(base[7]_reg_input, !GLOBAL(clock), , , base[7]_p3_out);


--A1L93Q is pwm~reg0
A1L93Q_p1_out = count[1] & count[2] & count[3] & count[4] & count[5] & count[7] & count[6];
A1L93Q_p2_out = !count[6] & base[7];
A1L93Q_p3_out = !count[7] & base[7];
A1L93Q_p4_out = !count[5] & base[7];
A1L93Q_or_out = A1L93Q_p1_out # A1L93Q_p2_out # A1L93Q_p3_out # A1L93Q_p4_out;
A1L93Q_reg_input = !(A1L93Q_or_out);
A1L93Q = DFFE(A1L93Q_reg_input, !GLOBAL(clock), , , );


--clock is clock
--operation mode is input

clock = INPUT();


--pwm is pwm
--operation mode is output

pwm = OUTPUT(A1L93Q);