lin.fit.eqn

verilog HDL 编写的PWM

--count1[23] is count1[23] at LC85
count1[23]_p1_out = count1[22] & count1[21] & count1[20] & count1[19] & count1[18] & count1[17] & count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[23]_or_out = count1[23];
count1[23]_reg_input = count1[23]_p1_out $ count1[23]_or_out;
count1[23] = DFFE(count1[23]_reg_input, !GLOBAL(clock), , , );


--count1[15] is count1[15] at LC14
count1[15]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L3 & F21L2 & !F21L1 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[15]_or_out = count1[15]_p1_out # !F51L8;
count1[15]_reg_input = !(count1[15]_or_out);
count1[15] = DFFE(count1[15]_reg_input, !GLOBAL(clock), , , );


--count1[7] is count1[7] at LC24
count1[7]_p1_out = count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count1[7]_or_out = count1[7];
count1[7]_reg_input = count1[7]_p1_out $ count1[7]_or_out;
count1[7] = DFFE(count1[7]_reg_input, !GLOBAL(clock), , , );


--count[7] is count[7] at LC6
count[7]_p1_out = count[6] & count[5] & count[4] & count[3] & count[2] & count[0] & count[1];
count[7]_p2_out = count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count[7];
count[7]_or_out = count[7]_p1_out # count[7]_p2_out;
count[7]_reg_input = count[7]_or_out;
count[7] = TFFE(count[7]_reg_input, !GLOBAL(clock), , , );


--count[1] is count[1] at LC5
count[1]_p1_out = count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count[1]_or_out = count[1]_p1_out # count[0];
count[1]_reg_input = count[1]_or_out;
count[1] = TFFE(count[1]_reg_input, !GLOBAL(clock), , , );


--F51L1 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[0]~64 at LC26
F51L1_p1_out = count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L1_or_out = !count1[8];
F51L1 = F51L1_p1_out $ F51L1_or_out;


--count[2] is count[2] at LC4
count[2]_p1_out = count[7] & count[6] & count[5] & count[4] & count[3] & count[1] & count[2];
count[2]_p2_out = count[1] & count[0];
count[2]_or_out = count[2]_p1_out # count[2]_p2_out;
count[2]_reg_input = count[2]_or_out;
count[2] = TFFE(count[2]_reg_input, !GLOBAL(clock), , , );


--count1[8] is count1[8] at LC12
count1[8]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L3 & F21L2 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L5 & F51L4 & !F51L3 & !F51L2 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[8]_or_out = count1[8]_p1_out # F51L1;
count1[8]_reg_input = !(count1[8]_or_out);
count1[8] = DFFE(count1[8]_reg_input, !GLOBAL(clock), , , );


--F51L2 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~68 at LC27
F51L2_p1_out = count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L2_or_out = count1[9];
F51L2 = F51L2_p1_out $ F51L2_or_out;


--count[3] is count[3] at LC3
count[3]_p1_out = count[7] & count[6] & count[5] & count[4] & count[2] & count[3] & count[1];
count[3]_p2_out = count[2] & count[1] & count[0];
count[3]_or_out = count[3]_p1_out # count[3]_p2_out;
count[3]_reg_input = count[3]_or_out;
count[3] = TFFE(count[3]_reg_input, !GLOBAL(clock), , , );


--count1[9] is count1[9] at LC23
count1[9]_p1_out = count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count1[9]_or_out = count1[9];
count1[9]_reg_input = count1[9]_p1_out $ count1[9]_or_out;
count1[9] = DFFE(count1[9]_reg_input, !GLOBAL(clock), , , );


--F51L3 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[2]~76 at LC28
F51L3_p1_out = count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L3_or_out = count1[10];
F51L3 = F51L3_p1_out $ F51L3_or_out;


--count1[10] is count1[10] at LC25
count1[10]_p1_out = count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count1[10]_or_out = count1[10];
count1[10]_reg_input = count1[10]_p1_out $ count1[10]_or_out;
count1[10] = DFFE(count1[10]_reg_input, !GLOBAL(clock), , , );


--count[4] is count[4] at LC2
count[4]_p1_out = count[7] & count[6] & count[5] & count[3] & count[4] & count[2] & count[1];
count[4]_p2_out = count[3] & count[2] & count[1] & count[0];
count[4]_or_out = count[4]_p1_out # count[4]_p2_out;
count[4]_reg_input = count[4]_or_out;
count[4] = TFFE(count[4]_reg_input, !GLOBAL(clock), , , );


--F51L4 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~84 at LC29
F51L4_p1_out = count1[10] & count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L4_or_out = count1[11];
F51L4 = F51L4_p1_out $ F51L4_or_out;


--count1[11] is count1[11] at LC15
count1[11]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L3 & F21L2 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L5 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[11]_or_out = count1[11]_p1_out # !F51L4;
count1[11]_reg_input = !(count1[11]_or_out);
count1[11] = DFFE(count1[11]_reg_input, !GLOBAL(clock), , , );


--count[5] is count[5] at LC1
count[5]_p1_out = count[7] & count[6] & count[4] & count[5] & count[3] & count[2] & count[1];
count[5]_p2_out = count[4] & count[3] & count[2] & count[1] & count[0];
count[5]_or_out = count[5]_p1_out # count[5]_p2_out;
count[5]_reg_input = count[5]_or_out;
count[5] = TFFE(count[5]_reg_input, !GLOBAL(clock), , , );


--F51L5 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[4]~88 at LC30
F51L5_p1_out = count1[11] & count1[10] & count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L5_or_out = count1[12];
F51L5 = F51L5_p1_out $ F51L5_or_out;


--count1[12] is count1[12] at LC13
count1[12]_p1_out = !F21L8 & !F21L7 & F21L6 & !F21L5 & F21L4 & F21L3 & F21L2 & !F21L1 & F51L8 & !F51L7 & !F51L6 & F51L4 & !F51L3 & !F51L2 & !F51L1 & !F81L8 & !F81L7 & !F81L6 & !F81L5 & !F81L4 & !F81L3 & !F81L2 & F81L1;
count1[12]_or_out = count1[12]_p1_out # !F51L5;
count1[12]_reg_input = !(count1[12]_or_out);
count1[12] = DFFE(count1[12]_reg_input, !GLOBAL(clock), , , );


--count[6] is count[6] at LC34
count[6]_p1_out = count[7] & count[5] & count[6] & count[4] & count[3] & count[2] & count[1];
count[6]_p2_out = count[5] & count[4] & count[3] & count[2] & count[1] & count[0];
count[6]_or_out = count[6]_p1_out # count[6]_p2_out;
count[6]_reg_input = count[6]_or_out;
count[6] = TFFE(count[6]_reg_input, !GLOBAL(clock), , , );


--F51L6 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[5]~92 at LC31
F51L6_p1_out = count1[12] & count1[11] & count1[10] & count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L6_or_out = count1[13];
F51L6 = F51L6_p1_out $ F51L6_or_out;


--count1[13] is count1[13] at LC20
count1[13]_p1_out = count1[12] & count1[11] & count1[10] & count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count1[13]_or_out = count1[13];
count1[13]_reg_input = count1[13]_p1_out $ count1[13]_or_out;
count1[13] = DFFE(count1[13]_reg_input, !GLOBAL(clock), , , );


--count[0] is count[0] at LC44
count[0]_p1_out = count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & !count[0];
count[0]_or_out = count[0]_p1_out;
count[0]_reg_input = !count[0]_or_out;
count[0] = TFFE(count[0]_reg_input, !GLOBAL(clock), , , );


--F51L7 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~100 at LC32
F51L7_p1_out = count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L7_or_out = count1[14];
F51L7 = F51L7_p1_out $ F51L7_or_out;


--F21L1 is lpm_add_sub:add_rtl_2|addcore:adder[0]|a_csnbuffer:result_node|sout_node[0]~66 at LC42
F21L1_p1_out = !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F21L1_or_out = !count1[0];
F21L1 = F21L1_p1_out $ F21L1_or_out;


--count1[14] is count1[14] at LC19
count1[14]_p1_out = count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
count1[14]_or_out = count1[14];
count1[14]_reg_input = count1[14]_p1_out $ count1[14]_or_out;
count1[14] = DFFE(count1[14]_reg_input, !GLOBAL(clock), , , );


--F51L8 is lpm_add_sub:add_rtl_2|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~108 at LC22
F51L8_p1_out = count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1];
F51L8_or_out = count1[15];
F51L8 = F51L8_p1_out $ F51L8_or_out;


--F81L1 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[0]~76 at LC88
F81L1_p1_out = count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L1_or_out = !count1[16];
F81L1 = F81L1_p1_out $ F81L1_or_out;


--count1[16] is count1[16] at LC18
count1[16]_p1_out = count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
count1[16]_or_out = count1[16]_p1_out;
count1[16]_reg_input = count1[16]_or_out;
count1[16] = TFFE(count1[16]_reg_input, !GLOBAL(clock), , , );


--F81L2 is lpm_add_sub:add_rtl_2|addcore:adder[2]|a_csnbuffer:result_node|sout_node[1]~83 at LC89
F81L2_p1_out = count1[16] & count1[7] & count1[6] & count1[5] & count1[4] & count1[3] & count1[2] & count1[1] & count1[0] & !count[0] & count[7] & count[6] & count[5] & count[4] & count[3] & count[2] & count[1] & count1[15] & count1[14] & count1[13] & count1[12] & count1[11] & count1[10] & count1[9] & count1[8];
F81L2_or_out = count1[17];
F81L2 = F81L2_p1_out $ F81L2_or_out;