sh4.inc
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· INC 代码 · 共 1,099 行 · 第 1/4 页
INC
1,099 行
;
; Copyright(c) 1998,1999 SIC/Hitachi,Ltd.
;
; Module Name:
;
; sh4.inc
;
; Revision History:
;
; 26th April 1999 Released
;
;
; CCN.
;
CCN_REGBASE .equ h'FF000000 ; CCN Register Base Address
CCN_REGSIZE .equ h'40
CCN_CCR_OFFSET .equ h'001C ; Cache Control Register Offset
CCN_QACR0_OFFSET .equ h'0038 ; Queue Address Control Register 0
CCN_QACR1_OFFSET .equ h'003C ; Queue Address Control Register 1
CCN_CCR .equ (CCN_REGBASE + CCN_CCR_OFFSET) ; Cache Control Register
CCN_QACR0 .equ (CCN_REGBASE + CCN_QACR0_OFFSET) ; Queue Address Control Register 0
CCN_QACR1 .equ (CCN_REGBASE + CCN_QACR1_OFFSET) ; Queue Address Control Register 1
; Cache Control Register
CCN_CCR_IIX .equ h'00008000 ;IC index mode
CCN_CCR_ICI .equ h'00000800 ;IC invalidation
CCN_CCR_ICE .equ h'00000100 ;IC enable
CCN_CCR_OIX .equ h'00000080 ;OC index mode
CCN_CCR_ORA .equ h'00000020 ;OC RAM enable
CCN_CCR_OCI .equ h'00000008 ;OC invalidation
CCN_CCR_CB .equ h'00000004 ;Copy-back enable
CCN_CCR_WT .equ h'00000002 ;Write-through enable
CCN_CCR_OCE .equ h'00000001 ;OC enable
;
; Bus state controller registers.
;
BSC_REGBASE .equ h'FF800000 ; Bus Stage Control Register Base Address
BSC_REGSIZE .equ h'2C ; Size of all of the BSC regs
BSC_BCR1_OFFSET .equ h'0000 ; Bus Control Register 1 Offset Address
BSC_BCR2_OFFSET .equ h'0004 ; Bus Control Register 2 Offset Address
BSC_WCR1_OFFSET .equ h'0008 ; Wait state Control Register 1 Offset Address
BSC_WCR2_OFFSET .equ h'000C ; Wait state Control Register 2 Offset Address
BSC_WCR3_OFFSET .equ h'0010 ; Wait state Control Register 3 Offset Address
BSC_MCR_OFFSET .equ h'0014 ; Individual Memory Control Register Offset Address
BSC_PCR_OFFSET .equ h'0018 ; PCMCIA Control Register Offset Address
BSC_RTCSR_OFFSET .equ h'001C ; Refresh Timer Control/Status Register Offset Address
BSC_RTCNT_OFFSET .equ h'0020 ; Refresh Timer Counter Offset Address
BSC_RTCOR_OFFSET .equ h'0024 ; Refresh Time Constant Register Offset Address
BSC_RFCR_OFFSET .equ h'0028 ; Refresh Count Register Offset Address
BSC_BCR1 .equ (BSC_REGBASE + BSC_BCR1_OFFSET) ; Bus Control Register 1 Offset Address
BSC_BCR2 .equ (BSC_REGBASE + BSC_BCR2_OFFSET) ; Bus Control Register 2 Offset Address
BSC_WCR1 .equ (BSC_REGBASE + BSC_WCR1_OFFSET) ; Wait state Control Register 1 Offset Address
BSC_WCR2 .equ (BSC_REGBASE + BSC_WCR2_OFFSET) ; Wait state Control Register 2 Offset Address
BSC_WCR3 .equ (BSC_REGBASE + BSC_WCR3_OFFSET) ; Wait state Control Register 3 Offset Address
BSC_MCR .equ (BSC_REGBASE + BSC_MCR_OFFSET) ; Individual Memory Control Register Offset Address
BSC_PCR .equ (BSC_REGBASE + BSC_PCR_OFFSET) ; PCMCIA Control Register Offset Address
BSC_RTCSR .equ (BSC_REGBASE + BSC_RTCSR_OFFSET) ; Refresh Timer Control/Status Register Offset Address
BSC_RTCNT .equ (BSC_REGBASE + BSC_RTCNT_OFFSET) ; Refresh Timer Counter Offset Address
BSC_RTCOR .equ (BSC_REGBASE + BSC_RTCOR_OFFSET) ; Refresh Time Constant Register Offset Address
BSC_RFCR .equ (BSC_REGBASE + BSC_RFCR_OFFSET) ; Refresh Count Register Offset Address
; BCR1 bus control register 1 fields (function and bus cycle status for each area).
BSC_BCR1_ENDIAN: .equ h'80000000 ; 1 <=> little endian
BSC_BCR1_MASTER: .equ h'40000000 ; 0:Master, 1:Slave
BSC_BCR1_A0MPX: .equ h'20000000 ; 0:SRAM, 1:MPX
BSC_BCR1_IPUP: .equ h'02000000 ; 0:pulled up, 1:not pulled up
BSC_BCR1_OPUP: .equ h'01000000 ; 0:pulled up, 1:not pulled up
BSC_BCR1_A1MBC: .equ h'00200000 ; 0:normal, 1:byte control mode
BSC_BCR1_A4MBC: .equ h'00100000 ; 0:normal, 1:byte control mode
BSC_BCR1_BREQEN: .equ h'00080000 ; BREQ Enable Bit
BSC_BCR1_PSHR: .equ h'00040000 ; Partial-Sharing Bit
BSC_BCR1_MEMMPX: .equ h'00020000 ; Area 1 to Area 6 MPX Bus Specification
BSC_BCR1_HIZMEM: .equ h'00008000 ; High-Z Control(HIZMEM)
BSC_BCR1_HIZCNT: .equ h'00004000 ; High-Z Control(HIZCNT)
BSC_BCR1_A0BST: .equ h'00003800 ; Area 0 burst mask
BSC_BCR1_A0BST_N: .equ h'00000000 ; Area 0 ordinary memory
BSC_BCR1_A0BST_4: .equ h'00000800 ; Area 0 burst (4 consecutive accesses)
BSC_BCR1_A0BST_8: .equ h'00001000 ; Area 0 burst (8 consecutive accesses)
BSC_BCR1_A0BST_16: .equ h'00001800 ; Area 0 burst (16 consecutive accesses)
BSC_BCR1_A0BST_32: .equ h'00002000 ; Area 0 burst (32 consecutive accesses)
BSC_BCR1_A5BST: .equ h'00000700 ; Area 5 burst mask
BSC_BCR1_A5BST_N: .equ h'00000000 ; Area 5 ordinary memory
BSC_BCR1_A5BST_4: .equ h'00000100 ; Area 5 burst (4 consecutive accesses)
BSC_BCR1_A5BST_8: .equ h'00000200 ; Area 5 burst (8 consecutive accesses)
BSC_BCR1_A5BST_16: .equ h'00000300 ; Area 5 burst (16 consecutive accesses)
BSC_BCR1_A5BST_32: .equ h'00000400 ; Area 5 burst (32 consecutive accesses)
BSC_BCR1_A6BST: .equ h'000000e0 ; Area 6 burst mask
BSC_BCR1_A6BST_N: .equ h'00000000 ; Area 6 ordinary memory
BSC_BCR1_A6BST_4: .equ h'00000020 ; Area 6 burst (4 consecutive accesses)
BSC_BCR1_A6BST_8: .equ h'00000040 ; Area 6 burst (8 consecutive accesses)
BSC_BCR1_A6BST_16: .equ h'00000060 ; Area 6 burst (16 consecutive accesses)
BSC_BCR1_A6BST_32: .equ h'00000080 ; Area 6 burst (32 consecutive accesses)
BSC_BCR1_DRAM: .equ h'0000001c ; Areas 2 & 3 mask
BSC_BCR1_DRAM_A2N3N: .equ h'00000000 ; Area 2 normal, Area 3 normal
BSC_BCR1_DRAM_A2N3P: .equ h'00000004 ; Area 2 normal, Area 3 PSRAM
BSC_BCR1_DRAM_A2N3S: .equ h'00000008 ; Area 2 normal, Area 3 SDRAM
BSC_BCR1_DRAM_A2S3S: .equ h'0000000c ; Area 2 SDRAM, Area 3 SDRAM
BSC_BCR1_DRAM_A2N3D: .equ h'00000010 ; Area 2 normal, Area 3 DRAM
BSC_BCR1_DRAM_A2D3D: .equ h'00000014 ; Area 2 DRAM, Area 3 DRAM
BSC_BCR1_A56PCM: .equ h'00000001
; BCR2: bus control register 2 fields. (bus size width of each area)
BSC_BCR2_A0SZ: .equ h'c000 ; Area 0 mask
BSC_BCR2_A0SZ_8: .equ h'4000 ; Area 0 is 8-bit memory
BSC_BCR2_A0SZ_16: .equ h'8000 ; Area 0 is 16-bit memory
BSC_BCR2_A0SZ_32: .equ h'c000 ; Area 0 is 32-bit memory
BSC_BCR2_A0SZ_64: .equ h'0000 ; Area 0 is 64-bit memory
BSC_BCR2_A6SZ: .equ h'3000 ; Area 6 mask
BSC_BCR2_A6SZ_8: .equ h'1000 ; Area 6 is 8-bit memory
BSC_BCR2_A6SZ_16: .equ h'2000 ; Area 6 is 16-bit memory
BSC_BCR2_A6SZ_32: .equ h'3000 ; Area 6 is 32-bit memory
BSC_BCR2_A6SZ_64: .equ h'0000 ; Area 6 is 64-bit memory
BSC_BCR2_A5SZ: .equ h'0c00 ; Area 5 mask
BSC_BCR2_A5SZ_8: .equ h'0400 ; Area 5 is 8-bit memory
BSC_BCR2_A5SZ_16: .equ h'0800 ; Area 5 is 16-bit memory
BSC_BCR2_A5SZ_32: .equ h'0c00 ; Area 5 is 32-bit memory
BSC_BCR2_A5SZ_64: .equ h'0000 ; Area 5 is 64-bit memory
BSC_BCR2_A4SZ: .equ h'0300 ; Area 4 mask
BSC_BCR2_A4SZ_8: .equ h'0100 ; Area 4 is 8-bit memory
BSC_BCR2_A4SZ_16: .equ h'0200 ; Area 4 is 16-bit memory
BSC_BCR2_A4SZ_32: .equ h'0300 ; Area 4 is 32-bit memory
BSC_BCR2_A4SZ_64: .equ h'0000 ; Area 4 is 64-bit memory
BSC_BCR2_A3SZ: .equ h'00c0 ; Area 3 mask
BSC_BCR2_A3SZ_8: .equ h'0040 ; Area 3 is 8-bit memory
BSC_BCR2_A3SZ_16: .equ h'0080 ; Area 3 is 16-bit memory
BSC_BCR2_A3SZ_32: .equ h'00c0 ; Area 3 is 32-bit memory
BSC_BCR2_A3SZ_64: .equ h'0000 ; Area 3 is 64-bit memory
BSC_BCR2_A2SZ: .equ h'0030 ; Area 2 mask
BSC_BCR2_A2SZ_8: .equ h'0010 ; Area 2 is 8-bit memory
BSC_BCR2_A2SZ_16: .equ h'0020 ; Area 2 is 16-bit memory
BSC_BCR2_A2SZ_32: .equ h'0030 ; Area 2 is 32-bit memory
BSC_BCR2_A2SZ_64: .equ h'0000 ; Area 2 is 64-bit memory
BSC_BCR2_A1SZ: .equ h'000c ; Area 1 mask
BSC_BCR2_A1SZ_8: .equ h'0004 ; Area 1 is 8-bit memory
BSC_BCR2_A1SZ_16: .equ h'0008 ; Area 1 is 16-bit memory
BSC_BCR2_A1SZ_32: .equ h'000c ; Area 1 is 32-bit memory
BSC_BCR2_A1SZ_64: .equ h'0000 ; Area 1 is 64-bit memory
BSC_BCR2_PORTEN: .equ h'0001 ; Port enable
; WCR1: Wait (idle) state control register 1 fields.
BSC_WCR1_DMAIW: .equ h'70000000 ;; DMA mask
BSC_WCR1_DMAIW_0: .equ h'00000000 ;; DMA has 0 idle states
BSC_WCR1_DMAIW_1: .equ h'10000000 ;; DMA has 1 idle states
BSC_WCR1_DMAIW_2: .equ h'20000000 ;; DMA has 2 idle states
BSC_WCR1_DMAIW_3: .equ h'30000000 ;; DMA has 3 idle states
BSC_WCR1_DMAIW_6: .equ h'40000000 ;; DMA has 6 idle states
BSC_WCR1_DMAIW_9: .equ h'50000000 ;; DMA has 9 idle states
BSC_WCR1_DMAIW_12: .equ h'60000000 ;; DMA has 12 idle states
BSC_WCR1_DMAIW_15: .equ h'70000000 ;; DMA has 15 idle states
BSC_WCR1_A6IW: .equ h'07000000 ; Area 6 mask
BSC_WCR1_A6IW_0: .equ h'00000000 ; Area 6 has 0 idle states
BSC_WCR1_A6IW_1: .equ h'01000000 ; Area 6 has 1 idle states
BSC_WCR1_A6IW_2: .equ h'02000000 ; Area 6 has 2 idle states
BSC_WCR1_A6IW_3: .equ h'03000000 ; Area 6 has 3 idle states
BSC_WCR1_A6IW_6: .equ h'04000000 ; Area 6 has 6 idle states
BSC_WCR1_A6IW_9: .equ h'05000000 ; Area 6 has 9 idle states
BSC_WCR1_A6IW_12: .equ h'06000000 ; Area 6 has 12 idle states
BSC_WCR1_A6IW_15: .equ h'07000000 ; Area 6 has 15 idle states
BSC_WCR1_A5IW: .equ h'00700000 ; Area 5 mask
BSC_WCR1_A5IW_0: .equ h'00000000 ; Area 5 has 0 idle states
BSC_WCR1_A5IW_1: .equ h'00100000 ; Area 5 has 1 idle states
BSC_WCR1_A5IW_2: .equ h'00200000 ; Area 5 has 2 idle states
BSC_WCR1_A5IW_3: .equ h'00300000 ; Area 5 has 3 idle states
BSC_WCR1_A5IW_6: .equ h'00400000 ; Area 5 has 6 idle states
BSC_WCR1_A5IW_9: .equ h'00500000 ; Area 5 has 9 idle states
BSC_WCR1_A5IW_12: .equ h'00600000 ; Area 5 has 12 idle states
BSC_WCR1_A5IW_15: .equ h'00700000 ; Area 5 has 15 idle states
BSC_WCR1_A4IW: .equ h'00070000 ; Area 4 mask
BSC_WCR1_A4IW_0: .equ h'00000000 ; Area 4 has 0 idle states
BSC_WCR1_A4IW_1: .equ h'00010000 ; Area 4 has 1 idle states
BSC_WCR1_A4IW_2: .equ h'00020000 ; Area 4 has 2 idle states
BSC_WCR1_A4IW_3: .equ h'00030000 ; Area 4 has 3 idle states
BSC_WCR1_A4IW_6: .equ h'00040000 ; Area 4 has 6 idle states
BSC_WCR1_A4IW_9: .equ h'00050000 ; Area 4 has 9 idle states
BSC_WCR1_A4IW_12: .equ h'00060000 ; Area 4 has 12 idle states
BSC_WCR1_A4IW_15: .equ h'00070000 ; Area 4 has 15 idle states
BSC_WCR1_A3IW: .equ h'00007000 ; Area 3 mask
BSC_WCR1_A3IW_0: .equ h'00000000 ; Area 3 has 0 idle states
BSC_WCR1_A3IW_1: .equ h'00001000 ; Area 3 has 1 idle states
BSC_WCR1_A3IW_2: .equ h'00002000 ; Area 3 has 2 idle states
BSC_WCR1_A3IW_3: .equ h'00003000 ; Area 3 has 3 idle states
BSC_WCR1_A3IW_6: .equ h'00004000 ; Area 3 has 6 idle states
BSC_WCR1_A3IW_9: .equ h'00005000 ; Area 3 has 9 idle states
BSC_WCR1_A3IW_12: .equ h'00006000 ; Area 3 has 12 idle states
BSC_WCR1_A3IW_15: .equ h'00007000 ; Area 3 has 15 idle states
BSC_WCR1_A2IW: .equ h'00000700 ; Area 2 mask
BSC_WCR1_A2IW_0: .equ h'00000000 ; Area 2 has 0 idle states
BSC_WCR1_A2IW_1: .equ h'00000100 ; Area 2 has 1 idle states
BSC_WCR1_A2IW_2: .equ h'00000200 ; Area 2 has 2 idle states
BSC_WCR1_A2IW_3: .equ h'00000300 ; Area 2 has 3 idle states
BSC_WCR1_A2IW_6: .equ h'00000400 ; Area 2 has 6 idle states
BSC_WCR1_A2IW_9: .equ h'00000500 ; Area 2 has 9 idle states
BSC_WCR1_A2IW_12: .equ h'00000600 ; Area 2 has 12 idle states
BSC_WCR1_A2IW_15: .equ h'00000700 ; Area 2 has 15 idle states
BSC_WCR1_A1IW: .equ h'00000070 ; Area 1 mask
BSC_WCR1_A1IW_0: .equ h'00000000 ; Area 1 has 0 idle states
BSC_WCR1_A1IW_1: .equ h'00000010 ; Area 1 has 1 idle states
BSC_WCR1_A1IW_2: .equ h'00000020 ; Area 1 has 2 idle states
BSC_WCR1_A1IW_3: .equ h'00000030 ; Area 1 has 3 idle states
BSC_WCR1_A1IW_6: .equ h'00000040 ; Area 1 has 6 idle states
BSC_WCR1_A1IW_9: .equ h'00000050 ; Area 1 has 9 idle states
BSC_WCR1_A1IW_12: .equ h'00000060 ; Area 1 has 12 idle states
BSC_WCR1_A1IW_15: .equ h'00000070 ; Area 1 has 15 idle states
BSC_WCR1_A0IW: .equ h'00000007 ; Area 0 mask
BSC_WCR1_A0IW_0: .equ h'00000000 ; Area 0 has 0 idle states
BSC_WCR1_A0IW_1: .equ h'00000001 ; Area 0 has 1 idle states
BSC_WCR1_A0IW_2: .equ h'00000002 ; Area 0 has 2 idle states
BSC_WCR1_A0IW_3: .equ h'00000003 ; Area 0 has 3 idle states
BSC_WCR1_A0IW_6: .equ h'00000004 ; Area 0 has 6 idle states
BSC_WCR1_A0IW_9: .equ h'00000005 ; Area 0 has 9 idle states
BSC_WCR1_A0IW_12: .equ h'00000006 ; Area 0 has 12 idle states
BSC_WCR1_A0IW_15: .equ h'00000007 ; Area 0 has 15 idle states
; WCR2: Wait state control register 2 fields.
BSC_WCR2_A6W: .equ h'e0000000 ; Area 6 wait state mask
BSC_WCR2_A6W_0: .equ h'00000000 ; Area 6 has 0 wait states
BSC_WCR2_A6W_1: .equ h'20000000 ; Area 6 has 1 wait states
BSC_WCR2_A6W_2: .equ h'40000000 ; Area 6 has 2 wait states
BSC_WCR2_A6W_3: .equ h'60000000 ; Area 6 has 3 wait states
BSC_WCR2_A6W_6: .equ h'80000000 ; Area 6 has 6 wait states
BSC_WCR2_A6W_9: .equ h'a0000000 ; Area 6 has 9 wait states
BSC_WCR2_A6W_12: .equ h'c0000000 ; Area 6 has 12 wait states
BSC_WCR2_A6W_15: .equ h'e0000000 ; Area 6 has 15 wait states
BSC_WCR2_A6B: .equ h'1c000000 ; Area 6 burst sycle mask
BSC_WCR2_A6B_0: .equ h'00000000 ; Area 6 has 0 states per data transfer
BSC_WCR2_A6B_1: .equ h'04000000 ; Area 6 has 1 states per data transfer
BSC_WCR2_A6B_2: .equ h'08000000 ; Area 6 has 2 states per data transfer
BSC_WCR2_A6B_3: .equ h'0c000000 ; Area 6 has 3 states per data transfer
BSC_WCR2_A6B_4: .equ h'10000000 ; Area 6 has 4 states per data transfer
BSC_WCR2_A6B_5: .equ h'14000000 ; Area 6 has 5 states per data transfer
BSC_WCR2_A6B_6: .equ h'18000000 ; Area 6 has 6 states per data transfer
BSC_WCR2_A6B_7: .equ h'1c000000 ; Area 6 has 7 states per data transfer
BSC_WCR2_A5W: .equ h'03800000 ; Area 5 wait state mask
BSC_WCR2_A5W_0: .equ h'00000000 ; Area 5 has 0 wait states
BSC_WCR2_A5W_1: .equ h'00800000 ; Area 5 has 1 wait states
BSC_WCR2_A5W_2: .equ h'01000000 ; Area 5 has 2 wait states
BSC_WCR2_A5W_3: .equ h'01800000 ; Area 5 has 3 wait states
BSC_WCR2_A5W_6: .equ h'02000000 ; Area 5 has 6 wait states
BSC_WCR2_A5W_9: .equ h'02800000 ; Area 5 has 9 wait states
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